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| author | Tom Rini <trini@konsulko.com> | 2019-03-10 10:16:07 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-03-10 10:16:07 -0400 |
| commit | 19c8c9c1031ebf345a68728d6f06d943207cea0f (patch) | |
| tree | 473081a243f14a82735242ef5e08cd9680a53a1d /arch/arm/mach-socfpga/misc.c | |
| parent | bdbf50f80c72b81c37a4fcdce5a92b21b790f888 (diff) | |
| parent | 88c3bb49e1bf2b808cbad1fbdeda09480ae580a7 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Arria10 DRAM fixes and Gen5 cache fixes
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index fcf211d62b..ec8339e045 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -62,8 +62,8 @@ void v7_outer_cache_enable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - writel(0x111, &pl310->pl310_tag_latency_ctrl); - writel(0x121, &pl310->pl310_data_latency_ctrl); + writel(0x0, &pl310->pl310_tag_latency_ctrl); + writel(0x10, &pl310->pl310_data_latency_ctrl); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, |