diff options
| author | Tom Rini <trini@konsulko.com> | 2019-05-05 12:25:39 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-05 12:25:39 -0400 |
| commit | abad176da14c576b5126484b03cba73a3b2c6f16 (patch) | |
| tree | 1baba7f9058acf8e41a043e6ce0f08dd1b94f644 /arch/arm/mach-socfpga/misc.c | |
| parent | 86f578ee85a697afb980233312f9aac1d98816df (diff) | |
| parent | 9337a08768dfa0a006382f1d05cf69b5f67f7844 (diff) | |
Merge branch '2019-05-05-master-imports'
- Various assorted fixes
- btrfs zstd compression support
- Enable hardware DDR levelling on am43xx platforms.
- pl310 cache controller driver
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index e1ea8eb73e..d887f0201f 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -59,20 +59,10 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x0, &pl310->pl310_tag_latency_ctrl); - writel(0x10, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); + struct udevice *dev; - /* Enable the L2 cache */ - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + if (uclass_get_device(UCLASS_CACHE, 0, &dev)) + pr_err("cache controller driver NOT found!\n"); } void v7_outer_cache_disable(void) |