diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2019-04-23 16:55:05 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-05 08:48:50 -0400 |
| commit | d97d8fcae59571c55485cba3749cae2114b7900e (patch) | |
| tree | 893f12f74192d14123348c1f7927305c02b65d23 /arch/arm/mach-socfpga/misc.c | |
| parent | 88ebf5830fe25cfdfbbee726cb36ea71b111173a (diff) | |
ARM: socfpga: use the pl310 driver to configure the cache
Find the UCLASS_CACHE driver to configure the cache controller's
settings.
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index e1ea8eb73e..d887f0201f 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -59,20 +59,10 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_enable(void) { - /* Disable the L2 cache */ - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - - writel(0x0, &pl310->pl310_tag_latency_ctrl); - writel(0x10, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); + struct udevice *dev; - /* Enable the L2 cache */ - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + if (uclass_get_device(UCLASS_CACHE, 0, &dev)) + pr_err("cache controller driver NOT found!\n"); } void v7_outer_cache_disable(void) |