diff options
| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2018-10-10 14:55:23 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-11-29 12:45:15 +0100 |
| commit | 30bade20a67a8205e10d006d8e1ac66552c1b137 (patch) | |
| tree | ce2fb3ff60042ffa0f9688e44d3df04230602549 /arch/arm/mach-socfpga/misc_gen5.c | |
| parent | e8dd60d489e19d12b193b945bb0d13ba40f9d8b0 (diff) | |
arm: socfpga: fix SPL booting from fpga OnChip RAM
This patch prevents disabling the FPGA bridges when
SPL or U-Boot is executed from FPGA onchip RAM.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/misc_gen5.c')
| -rw-r--r-- | arch/arm/mach-socfpga/misc_gen5.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..5fa40937c4 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -177,6 +177,8 @@ static void socfpga_nic301_slave_ns(void) void socfpga_sdram_remap_zero(void) { + u32 remap; + socfpga_nic301_slave_ns(); /* @@ -187,7 +189,12 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff); /* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + remap = 0x1; /* remap.mpuzero */ + /* Keep fpga bridge enabled when running from FPGA onchip RAM */ + if (socfpga_is_booting_from_fpga()) + remap |= 0x8; /* remap.hps2fpga */ + writel(remap, &nic301_regs->remap); + writel(0x1, &pl310->pl310_addr_filter_start); } |