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authorMarek Vasut <marex@denx.de>2015-07-09 03:52:12 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:06 +0200
commit292260ca21723ab78d23fa2cf6b574cf17778991 (patch)
treede81cb64cc73fbc523c4f06b07c039f58df17f1e /arch/arm/mach-socfpga/reset_manager.c
parenta71df7aa4fa775199280bba19072bd232cc35cb1 (diff)
arm: socfpga: reset: Repair bridge reset handling
The current bridge reset code, which de-asserted the bridge reset, was activelly polling whether the FPGA is programmed and ready and in case it was (!), the code called hang(). This makes no sense at all. Repair it such that the code instead checks whether the FPGA is programmed, but without any polling involved, and only if it is programmed, it de-asserts the reset. Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/mach-socfpga/reset_manager.c')
-rw-r--r--arch/arm/mach-socfpga/reset_manager.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 18af25ced1..6a11c19200 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -85,10 +85,10 @@ void socfpga_bridges_reset(int enable)
writel(0xffffffff, &reset_manager_base->brg_mod_reset);
} else {
/* Check signal from FPGA. */
- if (fpgamgr_poll_fpga_ready()) {
- /* FPGA not ready. Wait for watchdog timeout. */
- printf("%s: fpga not ready, hanging.\n", __func__);
- hang();
+ if (!fpgamgr_test_fpga_ready()) {
+ /* FPGA not ready, do nothing. */
+ printf("%s: FPGA not ready, aborting.\n", __func__);
+ return;
}
/* brdmodrst */