arm: socfpga: clock: Clean up pll_config.h

Extract the clock configuration horribleness caused by pll_config.h in
the following manner.

First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.

The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.

The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.

Signed-off-by: Marek Vasut <marex@denx.de>

1 files changed, 3 insertions, 111 deletions

diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 6850fbff15..1fecfdc4f7 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -23,31 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-#define MAIN_VCO_BASE (					\
-	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
-		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
-		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define PERI_VCO_BASE (					\
-	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
-		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
-		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
-		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define SDR_VCO_BASE (					\
-	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
-		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
-		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
-		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
 void board_init_f(ulong dummy)
 {
 	struct socfpga_system_manager *sysmgr_regs =
@@ -85,91 +60,8 @@ void spl_board_init(void)
 {
 	unsigned long sdram_size;
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-	struct cm_config cm_default_cfg = {
-		/* main group */
-		MAIN_VCO_BASE,
-		(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
-			CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
-			CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
-			CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
-			CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
-			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
-			CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
-			CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
-			CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
-			CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
-			CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
-			CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
-		/* peripheral group */
-		PERI_VCO_BASE,
-		(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
-			CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
-			CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
-			CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
-			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
-			CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
-			CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
-			CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
-			CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
-			CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
-			CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
-			CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
-			CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
-			CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
-			CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
-		/* sdram pll group */
-		SDR_VCO_BASE,
-		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
-			CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
-			CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
-		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
-			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
-			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
-		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
-			CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
-			CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
-		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
-			CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
-			CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-
-	};
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+#endif
 
 	debug("Freezing all I/O banks\n");
 	/* freeze all IO banks */
@@ -183,7 +75,7 @@ void spl_board_init(void)
 
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
-	cm_basic_init(&cm_default_cfg);
+	cm_basic_init(cm_default_cfg);
 
 	/* Enable bootrom to configure IOs. */
 	sysmgr_enable_warmrstcfgio();