diff options
author | Ley Foon Tan <ley.foon.tan@intel.com> | 2018-05-24 00:17:29 +0800 |
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committer | Marek Vasut <marex@denx.de> | 2018-07-12 09:22:12 +0200 |
commit | 73aede596cea7adc8e76dfbf92662cfc2eb0de5c (patch) | |
tree | 196c00f52e775eea5b0a03d1862268f80b85a17b /arch/arm/mach-socfpga/timer_s10.c | |
parent | 4765ddb0dab0ebd972f30725ca4397a93ee7272b (diff) |
arm: socfpga: stratix10: Add timer support for Stratix10 SoC
Add timer support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/mach-socfpga/timer_s10.c')
-rw-r--r-- | arch/arm/mach-socfpga/timer_s10.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c new file mode 100644 index 0000000000..57237892c3 --- /dev/null +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +/* + * Timer initialization + */ +int timer_init(void) +{ + int enable = 0x3; /* timer enable + output signal masked */ + int loadval = ~0; + + /* enable system counter */ + writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS); + /* enable processor pysical counter */ + asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); + asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); + + return 0; +} |