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| author | Paul Burton <paul.burton@imgtec.com> | 2016-05-27 14:28:05 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-05-31 09:44:24 +0200 |
| commit | 372286217f050bfd57695001d59f618c52822f40 (patch) | |
| tree | e2d926d936e6d65f2a229b19a347435f9f1d8d56 /arch/arm/mach-socfpga/wrap_iocsr_config.c | |
| parent | ace3be4f15875d74344336b9754c14274f940969 (diff) | |
MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/wrap_iocsr_config.c')
0 files changed, 0 insertions, 0 deletions