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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2017-07-03 18:37:11 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-08-09 09:57:32 -0700 |
| commit | bf7aecce04f0b29126b870c6d1e926bd26a681e8 (patch) | |
| tree | a695a2c27318a57c342f3683b92e4fbdf01854db /arch/arm/mach-socfpga/wrap_iocsr_config.c | |
| parent | 263536a693b3c3260f88b5e47a1d3e4962d66ba7 (diff) | |
armv8/fsl-lsch2: correct the config description of DSPI clock divider
It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/mach-socfpga/wrap_iocsr_config.c')
0 files changed, 0 insertions, 0 deletions