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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-12-31 15:48:48 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-01-03 09:47:10 -0500 |
| commit | 196d3e4017735c82cb5aa4387a9c44174a8391ac (patch) | |
| tree | 5ad1c12e357b17741276671db578f4cda6e5bb80 /arch/arm/mach-socfpga/wrap_pll_config_s10.c | |
| parent | c6ad93612ac90e99ae19103146d1128fef4030ea (diff) | |
arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config tool
Update the ddr settings to use the DDR reg config tool rev 0.2.0.
This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order
to avoid DSS underflow errors.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
Diffstat (limited to 'arch/arm/mach-socfpga/wrap_pll_config_s10.c')
0 files changed, 0 insertions, 0 deletions