diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-27 15:55:18 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 14:38:33 +0100 |
| commit | 2fd1dc5593d6ea0266797009dd702279fd10f7d1 (patch) | |
| tree | 628a901f5731bc663b0231a11c818b0c641b4e5c /arch/arm/mach-socfpga/wrap_pll_config_s10.c | |
| parent | 50278d4adea6f91e266c84e5df7ee3efa5aeb573 (diff) | |
arm: socfpga: Move Stratix10 and Agilex system manager common code
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/wrap_pll_config_s10.c')
| -rw-r--r-- | arch/arm/mach-socfpga/wrap_pll_config_s10.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index 2478321c27..b266a5817b 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -36,9 +36,10 @@ const unsigned int cm_get_osc_clk_hz(void) u32 clock = readl(S10_HANDOFF_CLOCK_OSC); writel(clock, - socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD1); + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); #endif - return readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD1); + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); } const unsigned int cm_get_intosc_clk_hz(void) @@ -52,7 +53,8 @@ const unsigned int cm_get_fpga_clk_hz(void) u32 clock = readl(S10_HANDOFF_CLOCK_FPGA); writel(clock, - socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD2); + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); #endif - return readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_BOOT_SCRATCH_COLD2); + return readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); } |