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authorDinh Nguyen <dinguyen@opensource.altera.com>2015-11-02 17:11:21 -0600
committerMarek Vasut <marex@denx.de>2015-11-03 17:32:16 +0100
commitc624d07f3ff7ae7d29672bab189d2aeb99c63a95 (patch)
treed1ace21fa5e8986683e6fbb282a8af07575869c0 /arch/arm/mach-socfpga
parent96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4 (diff)
arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines
The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga')
-rw-r--r--arch/arm/mach-socfpga/include/mach/reset_manager.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 8e59578f37..666a2ef8df 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -69,9 +69,9 @@ struct socfpga_reset_manager {
#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5)
-#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22)
-#define RSTMGR_DMA RSTMGR_DEFINE(0, 28)
+#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
/* Create a human-readable reference to SoCFPGA reset. */