diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2016-03-09 15:18:13 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-03-26 18:49:28 -0400 |
| commit | 9ecb0c416c68d3105bc9b6607bc8601cab2ecf35 (patch) | |
| tree | 049e372d9109963019def79dceebaf24d8713c2e /arch/arm/mach-stm32/stm32f4/clock.c | |
| parent | f9d0fd8a566f78f27a510258c34b3526f9822e92 (diff) | |
stm32: stm32f4: move flash driver to mtd driver location
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/mach-stm32/stm32f4/clock.c')
| -rw-r--r-- | arch/arm/mach-stm32/stm32f4/clock.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/arch/arm/mach-stm32/stm32f4/clock.c b/arch/arm/mach-stm32/stm32f4/clock.c index 631f36a5a1..15fcadbbe6 100644 --- a/arch/arm/mach-stm32/stm32f4/clock.c +++ b/arch/arm/mach-stm32/stm32f4/clock.c @@ -66,11 +66,6 @@ #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1) #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0) -#define FLASH_ACR_WS(n) n -#define FLASH_ACR_PRFTEN (1 << 8) -#define FLASH_ACR_ICEN (1 << 9) -#define FLASH_ACR_DCEN (1 << 10) - /* * RCC GPIO specific definitions */ @@ -181,10 +176,7 @@ int configure_clocks(void) while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) ; - /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */ - writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN - | FLASH_ACR_DCEN, &STM32_FLASH->acr); - + stm32_flash_latency_cfg(5); clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); |