diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-12-04 11:10:20 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-01-09 16:27:23 +0100 |
| commit | 52c2c97e7c5b3ba326bae53a7940e27878efd405 (patch) | |
| tree | ddb0de9dccc8eb634e9a46c9f0445d2ae664fb22 /arch/arm/mach-sunxi/clock_sun8i_a83t.c | |
| parent | b77e368fa27631f13c06acdb0020fb64b59d4411 (diff) | |
ARM: vf610: ddrmc: fix initialization completion detection
The CR80 register has multiple interrupt bits, the code is supposed
to check bit 8 but instead uses a logical and. In most cases this
probably did not affect real operations since at that stage typically
none of the other bits are set.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm/mach-sunxi/clock_sun8i_a83t.c')
0 files changed, 0 insertions, 0 deletions