diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2019-07-15 02:27:05 +0100 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-07-16 17:09:19 +0530 |
| commit | 65f80f58049a820e7d1ed7b0b0d233885ce6ebb2 (patch) | |
| tree | 383556a69976ea98c0300d79bcd69e715d0e5ec8 /arch/arm/mach-sunxi/dram_sun50i_h6.c | |
| parent | 1a1d1df384579e1323c72e8ba888ce45bfc4e781 (diff) | |
sunxi: H6: DRAM: follow recommended PHY init algorithm
The DRAM controller manual suggests to first program the PHY
initialisation parameters to the PHY_PIR register, and then set bit 0 to
trigger the initialisation. This is also used in boot0.
Follow this recommendation by setting bit 0 in a separate step.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/mach-sunxi/dram_sun50i_h6.c')
| -rw-r--r-- | arch/arm/mach-sunxi/dram_sun50i_h6.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index e2f141eb9b..7a8b724f08 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -75,12 +75,14 @@ static void mctl_core_init(struct dram_para *para) mctl_channel_init(para); } +/* PHY initialisation */ static void mctl_phy_pir_init(u32 val) { struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - writel(val | BIT(0), &mctl_phy->pir); + writel(val, &mctl_phy->pir); + writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */ mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0)); } |