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authorIcenowy Zheng <icenowy@aosc.io>2018-10-25 17:23:05 +0800
committerJagan Teki <jagan@amarulasolutions.com>2018-10-29 20:41:15 +0530
commit7009134c99512bd8a9a09cf14f35450f32a8602c (patch)
tree9ca64abbd8fb68aa6b78104b186db347e39bb33d /arch/arm/mach-sunxi
parentcff5c138495a4d68fa6e16953517087732b76662 (diff)
sunxi: map DRAM part with 3G size
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB. Change the size of DRAM part in MMU table to 3GiB. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
-rw-r--r--arch/arm/mach-sunxi/board.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index d22a84ea6b..b74eaf2a0e 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -52,7 +52,7 @@ static struct mm_region sunxi_mem_map[] = {
/* RAM */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
- .size = 0x80000000UL,
+ .size = 0xC0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {