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authorMichael Trimarchi <michael@amarulasolutions.com>2019-03-18 15:17:45 +0530
committerJagan Teki <jagan@amarulasolutions.com>2019-04-10 15:32:59 +0530
commitddd693021535b2ebd434b712c90443d95728cc8f (patch)
treeea580f0a158da554c242ca2b7f856f384bdb7e37 /arch/arm/mach-sunxi
parent30cb441ec69838cffe211cfde6ff6f7fa5a395cd (diff)
sunxi: dram_sun8i: Fix A33 memory initialization
While the exact problem is not known, based on discussion between Philipp Tomsich and André Przywara it is guessed that exit self-refresh timing is not set with correct value. There may be implicit enter or exit Self-Refresh anywhere as part of some training phase. In ZynqMP register guide [1], which is close to the various Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL tXS is bits [6:0]: Self refresh exit delay. So it could be safely increased and it only affects the time after the self-refresh “exit”, which happens only after (re-)initialisation. There was no document for cpu in question so based on oscilloscope readings [2][3] and observed result by comparing allwinner architecture. So set it same as Allwinner H5 silicon. Before this patch, failure rate of was 7%. This was tested on A33 allwinner cpu, dual rank connection connected with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3 1.5V And also this is tested in A33-OLinuXino dev board. [1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html [2] https://ibb.co/R70zmyS [3] https://ibb.co/HVVCGQ8 Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com> Acked-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
-rw-r--r--arch/arm/mach-sunxi/dram_sun8i_a33.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c
index 1da2727f98..5da01922bf 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_a33.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c
@@ -152,7 +152,7 @@ static void auto_set_timing_para(struct dram_para *para)
reg_val &= ~(0xff << 8);
reg_val &= ~(0xff << 0);
reg_val |= (0x33 << 8);
- reg_val |= (0x8 << 0);
+ reg_val |= (0x10 << 0);
writel(reg_val, &mctl_ctl->dramtmg8);
/* Set phy interface time */
reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)