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authorThierry Reding <treding@nvidia.com>2019-04-15 11:32:25 +0200
committerTom Warren <twarren@nvidia.com>2019-06-05 09:16:34 -0700
commitf9ec2ec8504aa5d94d5be7f43c743040e549b157 (patch)
tree7c68e815ecd3606853e85c899917ee3c95e91942 /arch/arm/mach-tegra/clock.c
parent147fac6aef043b41a48b3ad87639c6872da298f1 (diff)
ARM: tegra: Support TZ-only access to PMC
Some devices may restrict access to the PMC to TrustZone software only. Non-TZ software can detect this and use SMC calls to the firmware that runs in the TrustZone to perform accesses to PMC registers. Note that this also fixes reset_cpu() and the enterrcm command on Tegra186 where they were previously trying to access the PMC at a wrong physical address. Based on work by Kalyani Chidambaram <kalyanic@nvidia.com> and Tom Warren <twarren@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/clock.c')
-rw-r--r--arch/arm/mach-tegra/clock.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index dc5f16b41b..e539ad8b30 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
*/
/* Tegra SoC common clock control functions */
@@ -815,11 +815,16 @@ void tegra30_set_up_pllp(void)
int clock_external_output(int clk_id)
{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 val;
if (clk_id >= 1 && clk_id <= 3) {
- setbits_le32(&pmc->pmc_clk_out_cntrl,
- 1 << (2 + (clk_id - 1) * 8));
+ val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
+ pmc_clk_out_cntrl));
+ val |= 1 << (2 + (clk_id - 1) * 8);
+ tegra_pmc_writel(val,
+ offsetof(struct pmc_ctlr,
+ pmc_clk_out_cntrl));
+
} else {
printf("%s: Unknown output clock id %d\n", __func__, clk_id);
return -EINVAL;