diff options
| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 14:08:29 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-03-04 10:09:01 -0700 |
| commit | 790f7719e2635a3ff3f44473b060e01b5b5ebf74 (patch) | |
| tree | a93d85ab77323e2d6536a324c3ee84c1ae2685ad /arch/arm/mach-tegra/pinmux-common.c | |
| parent | f2c60eed513ecc142e0a39373d5c16a14f976d6d (diff) | |
ARM: tegra: pinmux: account for different drivegroup base registers
Tegra210 starts its drive group registers at a different offset from the
APB MISC register block that other SoCs. Update the code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pinmux-common.c')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux-common.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index b4ed153a2e..9bf3086971 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -99,7 +99,7 @@ #endif /* CONFIG_TEGRA20 */ -#define DRV_REG(group) _R(0x868 + ((group) * 4)) +#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4)) /* * We could force arch-tegraNN/pinmux.h to define all of these. However, |