ARM: tegra: collect SoC sources into mach-tegra

This commit moves files as follows:

 arch/arm/cpu/arm720t/tegra20/*      -> arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/arm720t/tegra30/*      -> arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/arm720t/tegra114/*     -> arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/arm720t/tegra124*      -> arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/arm720t/tegra-common/* -> arch/arm/mach-tegra/*
 arch/arm/cpu/armv7/tegra20/*        -> arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/armv7/tegra30/*        -> arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/armv7/tegra114/*       -> arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/armv7/tegra124/*       -> arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/armv7/tegra-common/*   -> arch/arm/mach-tegra/*
 arch/arm/cpu/tegra20-common/*       -> arch/arm/mach-tegra/tegra20/*
 arch/arm/cpu/tegra30-common/*       -> arch/arm/mach-tegra/tegra30/*
 arch/arm/cpu/tegra114-common/*      -> arch/arm/mach-tegra/tegra114/*
 arch/arm/cpu/tegra124-common/*      -> arch/arm/mach-tegra/tegra124/*
 arch/arm/cpu/tegra-common/*         -> arch/arm/mach-tegra/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Simon Glass <sjg@chromium.org> [ on nyan-big ]
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>

6 files changed, 1374 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig
new file mode 100644
index 0000000000..31012bc770
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114/Kconfig
@@ -0,0 +1,16 @@
+if TEGRA114
+
+choice
+	prompt "Tegra114 board select"
+
+config TARGET_DALMORE
+	bool "NVIDIA Tegra114 Dalmore evaluation board"
+
+endchoice
+
+config SYS_SOC
+	default "tegra114"
+
+source "board/nvidia/dalmore/Kconfig"
+
+endif
diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile
new file mode 100644
index 0000000000..7489f5f146
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114/Makefile
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+obj-$(CONFIG_SPL_BUILD) += cpu.o
+
+obj-y	+= clock.o funcmux.o pinmux.o
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
new file mode 100644
index 0000000000..d5194e11b5
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -0,0 +1,669 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra114 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+	CLOCK_TYPE_AXPT,	/* PLL_A, PLL_X, PLL_P, CLK_M */
+	CLOCK_TYPE_MCPA,	/* and so on */
+	CLOCK_TYPE_MCPT,
+	CLOCK_TYPE_PCM,
+	CLOCK_TYPE_PCMT,
+	CLOCK_TYPE_PCMT16,
+	CLOCK_TYPE_PDCT,
+	CLOCK_TYPE_ACPT,
+	CLOCK_TYPE_ASPTE,
+	CLOCK_TYPE_PMDACD2T,
+	CLOCK_TYPE_PCST,
+
+	CLOCK_TYPE_COUNT,
+	CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+	CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_30},
+	{ CLK(AUDIO),	CLK(SFROM32KHZ),	CLK(PERIPH),	CLK(OSC),
+		CLK(EPCI),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(MEMORY),	CLK(DISPLAY),	CLK(AUDIO),
+		CLK(CGENERAL),	CLK(DISPLAY2),	CLK(OSC),	CLK(NONE),
+		MASK_BITS_31_29},
+	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(SFROM32KHZ),	CLK(OSC),
+		CLK(NONE),	CLK(NONE),	CLK(NONE),	CLK(NONE),
+		MASK_BITS_31_28}
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+	/* 0x00 */
+	TYPE(PERIPHC_I2S1,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S2,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_OUT,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_SPDIF_IN,	CLOCK_TYPE_PCM),
+	TYPE(PERIPHC_PWM,	CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x08 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_I2C1,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_I2C5,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_DISP1,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_DISP2,	CLOCK_TYPE_PMDACD2T),
+
+	/* 0x10 */
+	TYPE(PERIPHC_CVE,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SDMMC1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC2,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_G3D,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_G2D,	CLOCK_TYPE_MCPA),
+
+	/* 0x18 */
+	TYPE(PERIPHC_NDFLASH,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SDMMC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VFIR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_EPP,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MPE,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MIPI,	CLOCK_TYPE_PCMT),	/* MIPI base-band HSI */
+	TYPE(PERIPHC_UART1,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART2,	CLOCK_TYPE_PCMT),
+
+	/* 0x20 */
+	TYPE(PERIPHC_HOST1X,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVO,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_HDMI,	CLOCK_TYPE_PMDACD2T),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_TVDAC,	CLOCK_TYPE_PDCT),
+	TYPE(PERIPHC_I2C2,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_EMC,	CLOCK_TYPE_MCPT),
+
+	/* 0x28 */
+	TYPE(PERIPHC_UART3,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_VI,	CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SBC4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2C3,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SDMMC3,	CLOCK_TYPE_PCMT),
+
+	/* 0x30 */
+	TYPE(PERIPHC_UART4,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_UART5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_VDE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_OWR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NOR,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_CSITE,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
+
+	/* 0x38h */  /* Jumps to reg offset 0x3B0h */
+	TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
+	TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),	/* s/b PCTS */
+	TYPE(PERIPHC_I2S3,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2S4,	CLOCK_TYPE_AXPT),
+	TYPE(PERIPHC_I2C4,	CLOCK_TYPE_PCMT16),
+	TYPE(PERIPHC_SBC5,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_SBC6,	CLOCK_TYPE_PCMT),
+
+	/* 0x40 */
+	TYPE(PERIPHC_AUDIO,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_DAM0,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM1,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_DAM2,	CLOCK_TYPE_ACPT),
+	TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_ACTMON,	CLOCK_TYPE_PCST),	/* MASK 31:30 */
+	TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+	/* 0x48 */
+	TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+	TYPE(PERIPHC_NANDSPEED,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_I2CSLOW,	CLOCK_TYPE_PCST),	/* MASK 31:30 */
+	TYPE(PERIPHC_SYS,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SPEEDO,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+
+	/* 0x50 */
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_NONE,	CLOCK_TYPE_NONE),
+	TYPE(PERIPHC_SATAOOB,	CLOCK_TYPE_PCMT),	/* offset 0x420h */
+	TYPE(PERIPHC_SATA,	CLOCK_TYPE_PCMT),
+	TYPE(PERIPHC_HDA,	CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *	uint vi_sensor;	 _VI_SENSOR_0,		0x1A8
+ *	SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+	/* Low word: 31:0 */
+	NONE(CPU),
+	NONE(COP),
+	NONE(TRIGSYS),
+	NONE(RESERVED3),
+	NONE(RTC),
+	NONE(TMR),
+	PERIPHC_UART1,
+	PERIPHC_UART2,	/* and vfir 0x68 */
+
+	/* 8 */
+	NONE(GPIO),
+	PERIPHC_SDMMC2,
+	NONE(SPDIF),		/* 0x08 and 0x0c, unclear which to use */
+	PERIPHC_I2S1,
+	PERIPHC_I2C1,
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC4,
+
+	/* 16 */
+	NONE(RESERVED16),
+	PERIPHC_PWM,
+	PERIPHC_I2S2,
+	PERIPHC_EPP,
+	PERIPHC_VI,
+	PERIPHC_G2D,
+	NONE(USBD),
+	NONE(ISP),
+
+	/* 24 */
+	PERIPHC_G3D,
+	NONE(RESERVED25),
+	PERIPHC_DISP2,
+	PERIPHC_DISP1,
+	PERIPHC_HOST1X,
+	NONE(VCP),
+	PERIPHC_I2S0,
+	NONE(CACHE2),
+
+	/* Middle word: 63:32 */
+	NONE(MEM),
+	NONE(AHBDMA),
+	NONE(APBDMA),
+	NONE(RESERVED35),
+	NONE(RESERVED36),
+	NONE(STAT_MON),
+	NONE(RESERVED38),
+	NONE(RESERVED39),
+
+	/* 40 */
+	NONE(KFUSE),
+	NONE(SBC1),	/* SBC1, 0x34, is this SPI1? */
+	PERIPHC_NOR,
+	NONE(RESERVED43),
+	PERIPHC_SBC2,
+	NONE(RESERVED45),
+	PERIPHC_SBC3,
+	PERIPHC_I2C5,
+
+	/* 48 */
+	NONE(DSI),
+	PERIPHC_TVO,	/* also CVE 0x40 */
+	PERIPHC_MIPI,
+	PERIPHC_HDMI,
+	NONE(CSI),
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_UART3,
+
+	/* 56 */
+	NONE(RESERVED56),
+	PERIPHC_EMC,
+	NONE(USB2),
+	NONE(USB3),
+	PERIPHC_MPE,
+	PERIPHC_VDE,
+	NONE(BSEA),
+	NONE(BSEV),
+
+	/* Upper word 95:64 */
+	PERIPHC_SPEEDO,
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_I2C3,
+	PERIPHC_SBC4,
+	PERIPHC_SDMMC3,
+	NONE(PCIE),
+	PERIPHC_OWR,
+
+	/* 72 */
+	NONE(AFI),
+	PERIPHC_CSITE,
+	NONE(PCIEXCLK),
+	NONE(AVPUCQ),
+	NONE(RESERVED76),
+	NONE(RESERVED77),
+	NONE(RESERVED78),
+	NONE(DTV),
+
+	/* 80 */
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	NONE(DSIB),
+	NONE(RESERVED83),
+	NONE(IRAMA),
+	NONE(IRAMB),
+	NONE(IRAMC),
+	NONE(IRAMD),
+
+	/* 88 */
+	NONE(CRAM2),
+	NONE(RESERVED89),
+	NONE(MDOUBLER),
+	NONE(RESERVED91),
+	NONE(SUSOUT),
+	NONE(RESERVED93),
+	NONE(RESERVED94),
+	NONE(RESERVED95),
+
+	/* V word: 31:0 */
+	NONE(CPUG),
+	NONE(CPULP),
+	PERIPHC_G3D2,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+
+	/* 08 */
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+	PERIPHC_AUDIO,
+	NONE(APBIF),
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+
+	/* 16 */
+	NONE(ATOMICS),
+	NONE(RESERVED17),
+	NONE(RESERVED18),
+	NONE(RESERVED19),
+	NONE(RESERVED20),
+	NONE(RESERVED21),
+	NONE(RESERVED22),
+	PERIPHC_ACTMON,
+
+	/* 24 */
+	NONE(RESERVED24),
+	NONE(RESERVED25),
+	NONE(RESERVED26),
+	NONE(RESERVED27),
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+	NONE(RESERVED30),
+	NONE(RESERVED31),
+
+	/* W word: 31:0 */
+	NONE(HDA2HDMICODEC),
+	NONE(RESERVED1_SATACOLD),
+	NONE(RESERVED2_PCIERX0),
+	NONE(RESERVED3_PCIERX1),
+	NONE(RESERVED4_PCIERX2),
+	NONE(RESERVED5_PCIERX3),
+	NONE(RESERVED6_PCIERX4),
+	NONE(RESERVED7_PCIERX5),
+
+	/* 40 */
+	NONE(CEC),
+	NONE(PCIE2_IOBIST),
+	NONE(EMC_IOBIST),
+	NONE(HDMI_IOBIST),
+	NONE(SATA_IOBIST),
+	NONE(MIPI_IOBIST),
+	NONE(EMC1_IOBIST),
+	NONE(XUSB),
+
+	/* 48 */
+	NONE(CILAB),
+	NONE(CILCD),
+	NONE(CILE),
+	NONE(DSIA_LP),
+	NONE(DSIB_LP),
+	NONE(RESERVED21_ENTROPY),
+	NONE(RESERVED22_W),
+	NONE(RESERVED23_W),
+
+	/* 56 */
+	NONE(RESERVED24_W),
+	NONE(AMX0),
+	NONE(ADX0),
+	NONE(DVFS),
+	NONE(XUSB_SS),
+	NONE(EMC_DLL),
+	NONE(MC1),
+	NONE(EMC1),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that T30/T114 support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	reg = readl(&clkrst->crc_osc_ctrl);
+	reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+	if (reg & 1)				/* one of the newer freqs */
+		printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+	return reg >> 2;	/* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	enum periphc_internal_id internal_id;
+
+	/* Coresight is a special case */
+	if (periph_id == PERIPH_ID_CSI)
+		return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+	assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(internal_id != -1);
+	if (internal_id >= PERIPHC_VW_FIRST) {
+		internal_id -= PERIPHC_VW_FIRST;
+		return &clkrst->crc_clk_src_vw[internal_id];
+	} else
+		return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id	peripheral to start
+ * @param source	PLL id of required parent clock
+ * @param mux_bits	Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+	enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+	enum clock_type_id type;
+	enum periphc_internal_id internal_id;
+	int mux;
+
+	assert(clock_periph_id_isvalid(periph_id));
+
+	internal_id = periph_id_to_internal_id[periph_id];
+	assert(periphc_internal_id_isvalid(internal_id));
+
+	type = clock_periph_type[internal_id];
+	assert(clock_type_id_isvalid(type));
+
+	*mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+	if (type == CLOCK_TYPE_PCMT16)
+		*divider_bits = 16;
+	else
+		*divider_bits = 8;
+
+	for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+		if (clock_source[type][mux] == parent)
+			return mux;
+
+	/* if we get here, either us or the caller has made a mistake */
+	printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+		parent);
+	return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *clk;
+	u32 reg;
+
+	/* Enable/disable the clock to this peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+		clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+	else
+		clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+	reg = readl(clk);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 *reset;
+	u32 reg;
+
+	/* Enable/disable reset to the peripheral */
+	assert(clock_periph_id_isvalid(periph_id));
+	if (periph_id < PERIPH_ID_VW_FIRST)
+		reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+	else
+		reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+	reg = readl(reset);
+	if (enable)
+		reg |= PERIPH_MASK(periph_id);
+	else
+		reg &= ~PERIPH_MASK(periph_id);
+	writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id    Clock ID according to tegra114 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+	if (clk_id > PERIPH_ID_COUNT)
+		return PERIPH_ID_NONE;
+
+	switch (clk_id) {
+	case PERIPH_ID_RESERVED3:
+	case PERIPH_ID_RESERVED16:
+	case PERIPH_ID_RESERVED24:
+	case PERIPH_ID_RESERVED35:
+	case PERIPH_ID_RESERVED43:
+	case PERIPH_ID_RESERVED45:
+	case PERIPH_ID_RESERVED56:
+	case PERIPH_ID_RESERVED76:
+	case PERIPH_ID_RESERVED77:
+	case PERIPH_ID_RESERVED78:
+	case PERIPH_ID_RESERVED83:
+	case PERIPH_ID_RESERVED89:
+	case PERIPH_ID_RESERVED91:
+	case PERIPH_ID_RESERVED93:
+	case PERIPH_ID_RESERVED94:
+	case PERIPH_ID_RESERVED95:
+		return PERIPH_ID_NONE;
+	default:
+		return clk_id;
+	}
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+	struct clk_rst_ctlr *clkrst =
+		(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+	tegra30_set_up_pllp();
+
+	/*
+	 * PLLC output frequency set to 600Mhz
+	 * PLLD output frequency set to 925Mhz
+	 */
+	switch (clock_get_osc_freq()) {
+	case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+		break;
+
+	case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+		clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+		clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+		break;
+	case CLOCK_OSC_FREQ_19_2:
+	default:
+		/*
+		 * These are not supported. It is too early to print a
+		 * message and the UART likely won't work anyway due to the
+		 * oscillator being wrong.
+		 */
+		break;
+	}
+
+	/* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+	writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+	/* PLLC_MISC: Set LOCK_ENABLE */
+	writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+	udelay(2);
+
+	/* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+	writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+	udelay(2);
+}
+
+void arch_timer_init(void)
+{
+	struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+	u32 freq, val;
+
+	freq = clock_get_rate(CLOCK_ID_OSC);
+	debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+	/* ARM CNTFRQ */
+	asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+	/* Only T114 has the System Counter regs */
+	debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+	writel(freq, &sysctr->cntfid0);
+
+	val = readl(&sysctr->cntcr);
+	val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+	writel(val, &sysctr->cntcr);
+	debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/arch/arm/mach-tegra/tegra114/cpu.c b/arch/arm/mach-tegra/tegra114/cpu.c
new file mode 100644
index 0000000000..18dc1af1b4
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114/cpu.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include "../cpu.h"
+
+/* Tegra114-specific CPU init code */
+static void enable_cpu_power_rail(void)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_power_rail entry\n");
+
+	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
+
+	/*
+	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+	 * set it for 25ms (102MHz * .025)
+	 */
+	reg = 0x26E8F0;
+	writel(reg, &pmc->pmc_cpupwrgood_timer);
+
+	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+
+	/*
+	 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
+	 * to 408 to satisfy the requirement of having at least 16 CPU clock
+	 * cycles before clamp removal.
+	 */
+
+	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
+	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
+}
+
+static void enable_cpu_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("enable_cpu_clocks entry\n");
+
+	/* Wait for PLL-X to lock */
+	do {
+		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+	} while ((reg & PLL_LOCK_MASK) == 0);
+
+	/* Wait until all clocks are stable */
+	udelay(PLL_STABILIZATION_DELAY);
+
+	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+	/* Always enable the main CPU complex clocks */
+	clock_enable(PERIPH_ID_CPU);
+	clock_enable(PERIPH_ID_CPULP);
+	clock_enable(PERIPH_ID_CPUG);
+}
+
+static void remove_cpu_resets(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	u32 reg;
+
+	debug("remove_cpu_resets entry\n");
+	/* Take the slow non-CPU partition out of reset */
+	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Take the fast non-CPU partition out of reset */
+	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the slow cluster */
+	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+	/* Clear the SW-controlled reset of the fast cluster */
+	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+	reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
+	reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
+	reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
+	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The T114 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void t114_init_clocks(void)
+{
+	struct clk_rst_ctlr *clkrst =
+			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	u32 val;
+
+	debug("t114_init_clocks entry\n");
+
+	/* Set active CPU cluster to G */
+	clrbits_le32(&flow->cluster_control, 1);
+
+	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+	debug("Setting up PLLX\n");
+	init_pllx();
+
+	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+	writel(val, &clkrst->crc_clk_sys_rate);
+
+	/* Enable clocks to required peripherals. TBD - minimize this list */
+	debug("Enabling clocks\n");
+
+	clock_set_enable(PERIPH_ID_CACHE2, 1);
+	clock_set_enable(PERIPH_ID_GPIO, 1);
+	clock_set_enable(PERIPH_ID_TMR, 1);
+	clock_set_enable(PERIPH_ID_RTC, 1);
+	clock_set_enable(PERIPH_ID_CPU, 1);
+	clock_set_enable(PERIPH_ID_EMC, 1);
+	clock_set_enable(PERIPH_ID_I2C5, 1);
+	clock_set_enable(PERIPH_ID_FUSE, 1);
+	clock_set_enable(PERIPH_ID_PMC, 1);
+	clock_set_enable(PERIPH_ID_APBDMA, 1);
+	clock_set_enable(PERIPH_ID_MEM, 1);
+	clock_set_enable(PERIPH_ID_IRAMA, 1);
+	clock_set_enable(PERIPH_ID_IRAMB, 1);
+	clock_set_enable(PERIPH_ID_IRAMC, 1);
+	clock_set_enable(PERIPH_ID_IRAMD, 1);
+	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+	clock_set_enable(PERIPH_ID_MSELECT, 1);
+	clock_set_enable(PERIPH_ID_EMC1, 1);
+	clock_set_enable(PERIPH_ID_MC1, 1);
+	clock_set_enable(PERIPH_ID_DVFS, 1);
+
+	/*
+	 * Set MSELECT clock source as PLLP (00), and ask for a clock
+	 * divider that would set the MSELECT clock at 102MHz for a
+	 * PLLP base of 408MHz.
+	 */
+	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+		CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+	/* Give clocks time to stabilize */
+	udelay(1000);
+
+	/* Take required peripherals out of reset */
+	debug("Taking periphs out of reset\n");
+	reset_set_enable(PERIPH_ID_CACHE2, 0);
+	reset_set_enable(PERIPH_ID_GPIO, 0);
+	reset_set_enable(PERIPH_ID_TMR, 0);
+	reset_set_enable(PERIPH_ID_COP, 0);
+	reset_set_enable(PERIPH_ID_EMC, 0);
+	reset_set_enable(PERIPH_ID_I2C5, 0);
+	reset_set_enable(PERIPH_ID_FUSE, 0);
+	reset_set_enable(PERIPH_ID_APBDMA, 0);
+	reset_set_enable(PERIPH_ID_MEM, 0);
+	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+	reset_set_enable(PERIPH_ID_MSELECT, 0);
+	reset_set_enable(PERIPH_ID_EMC1, 0);
+	reset_set_enable(PERIPH_ID_MC1, 0);
+	reset_set_enable(PERIPH_ID_DVFS, 0);
+
+	debug("t114_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get power gate status */
+	reg = readl(&pmc->pmc_pwrgate_status);
+	return !!(reg & (1 << partid));
+}
+
+static bool is_clamp_enabled(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	/* Get clamp status. */
+	reg = readl(&pmc->pmc_clamp_status);
+	return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+	debug("%s: part ID = %08X\n", __func__, partid);
+	/* Is the partition already on? */
+	if (!is_partition_powered(partid)) {
+		/* No, toggle the partition power state (OFF -> ON) */
+		debug("power_partition, toggling state\n");
+		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+		/* Wait for the power to come up */
+		while (!is_partition_powered(partid))
+			;
+
+		/* Wait for the clamp status to be cleared */
+		while (is_clamp_enabled(partid))
+			;
+
+		/* Give I/O signals time to stabilize */
+		udelay(IO_STABILIZATION_DELAY);
+	}
+}
+
+void powerup_cpus(void)
+{
+	debug("powerup_cpus entry\n");
+
+	/* We boot to the fast cluster */
+	debug("powerup_cpus entry: G cluster\n");
+	/* Power up the fast cluster rail partition */
+	power_partition(CRAIL);
+
+	/* Power up the fast cluster non-CPU partition */
+	power_partition(C0NC);
+
+	/* Power up the fast cluster CPU0 partition */
+	power_partition(CE0);
+}
+
+void start_cpu(u32 reset_vector)
+{
+	u32 imme, inst;
+
+	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+	t114_init_clocks();
+
+	/* Enable VDD_CPU */
+	enable_cpu_power_rail();
+
+	/* Get the CPU(s) running */
+	enable_cpu_clocks();
+
+	/* Enable CoreSight */
+	clock_enable_coresight(1);
+
+	/* Take CPU(s) out of reset */
+	remove_cpu_resets();
+
+	/* Set the entry point for CPU execution from reset */
+
+	/*
+	 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
+	 * See nvbug 1193357 for details.
+	 */
+
+	/* mov r0, #lsb(reset_vector) */
+	imme = reset_vector & 0xffff;
+	inst = imme & 0xfff;
+	inst |= ((imme >> 12) << 16);
+	inst |= 0xe3000000;
+	writel(inst, 0x4003fff0);
+
+	/* movt r0, #msb(reset_vector) */
+	imme = (reset_vector >> 16) & 0xffff;
+	inst = imme & 0xfff;
+	inst |= ((imme >> 12) << 16);
+	inst |= 0xe3400000;
+	writel(inst, 0x4003fff4);
+
+	/* bx r0 */
+	writel(0xe12fff10, 0x4003fff8);
+
+	/* b -12 */
+	imme = (u32)-20;
+	inst = (imme >> 2) & 0xffffff;
+	inst |= 0xea000000;
+	writel(inst, 0x4003fffc);
+
+	/* Write to orignal location for compatibility */
+	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* If the CPU(s) don't already have power, power 'em up */
+	powerup_cpus();
+}
diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c
new file mode 100644
index 0000000000..52441c71e6
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114/funcmux.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	int bad_config = config != FUNCMUX_DEFAULT;
+
+	switch (id) {
+	case PERIPH_ID_UART4:
+		switch (config) {
+		case FUNCMUX_UART4_GMI:
+			pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
+					PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
+					PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
+					PMUX_FUNC_UARTD);
+			pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
+					PMUX_FUNC_UARTD);
+
+			pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
+			pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
+			pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
+			pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
+
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
+			pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
+			break;
+		}
+		break;
+
+	/* Add other periph IDs here as needed */
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	if (bad_config) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra114/pinmux.c b/arch/arm/mach-tegra/tegra114/pinmux.c
new file mode 100644
index 0000000000..3e5acb93ce
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114/pinmux.c
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+#define PIN(pin, f0, f1, f2, f3)	\
+	{				\
+		.funcs = {		\
+			PMUX_FUNC_##f0,	\
+			PMUX_FUNC_##f1,	\
+			PMUX_FUNC_##f2,	\
+			PMUX_FUNC_##f3,	\
+		},			\
+	}
+
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra114_pingroups[] = {
+	/*  pin,                    f0,         f1,       f2,           f3 */
+	/* Offset 0x3000 */
+	PIN(ULPI_DATA0_PO1,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA1_PO2,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA2_PO3,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA3_PO4,         SPI3,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA4_PO5,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA5_PO6,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA6_PO7,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_DATA7_PO0,         SPI2,       HSI,      UARTA,        ULPI),
+	PIN(ULPI_CLK_PY0,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_DIR_PY1,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_NXT_PY2,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(ULPI_STP_PY3,           SPI1,       SPI5,     UARTD,        ULPI),
+	PIN(DAP3_FS_PP0,            I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_DIN_PP1,           I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_DOUT_PP2,          I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(DAP3_SCLK_PP3,          I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+	PIN(PV0,                    USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PV1,                    RSVD1,      RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC1_CLK_PZ0,         SDMMC1,     CLK12,    RSVD3,        RSVD4),
+	PIN(SDMMC1_CMD_PZ1,         SDMMC1,     SPDIF,    SPI4,         UARTA),
+	PIN(SDMMC1_DAT3_PY4,        SDMMC1,     SPDIF,    SPI4,         UARTA),
+	PIN(SDMMC1_DAT2_PY5,        SDMMC1,     PWM0,     SPI4,         UARTA),
+	PIN(SDMMC1_DAT1_PY6,        SDMMC1,     PWM1,     SPI4,         UARTA),
+	PIN(SDMMC1_DAT0_PY7,        SDMMC1,     RSVD2,    SPI4,         UARTA),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3068 */
+	PIN(CLK2_OUT_PW5,           EXTPERIPH2, RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK2_REQ_PCC5,          DAP,        RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3110 */
+	PIN(HDMI_INT_PN7,           RSVD1,      RSVD2,    RSVD3,        RSVD4),
+	PIN(DDC_SCL_PV4,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DDC_SDA_PV5,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3164 */
+	PIN(UART2_RXD_PC3,          IRDA,       SPDIF,    UARTA,        SPI4),
+	PIN(UART2_TXD_PC2,          IRDA,       SPDIF,    UARTA,        SPI4),
+	PIN(UART2_RTS_N_PJ6,        UARTA,      UARTB,    RSVD3,        SPI4),
+	PIN(UART2_CTS_N_PJ5,        UARTA,      UARTB,    RSVD3,        SPI4),
+	PIN(UART3_TXD_PW6,          UARTC,      RSVD2,    RSVD3,        SPI4),
+	PIN(UART3_RXD_PW7,          UARTC,      RSVD2,    RSVD3,        SPI4),
+	PIN(UART3_CTS_N_PA1,        UARTC,      SDMMC1,   DTV,          SPI4),
+	PIN(UART3_RTS_N_PC0,        UARTC,      PWM0,     DTV,          DISPLAYA),
+	PIN(PU0,                    OWR,        UARTA,    RSVD3,        RSVD4),
+	PIN(PU1,                    RSVD1,      UARTA,    RSVD3,        RSVD4),
+	PIN(PU2,                    RSVD1,      UARTA,    RSVD3,        RSVD4),
+	PIN(PU3,                    PWM0,       UARTA,    DISPLAYA,     DISPLAYB),
+	PIN(PU4,                    PWM1,       UARTA,    DISPLAYA,     DISPLAYB),
+	PIN(PU5,                    PWM2,       UARTA,    DISPLAYA,     DISPLAYB),
+	PIN(PU6,                    PWM3,       UARTA,    USB,          DISPLAYB),
+	PIN(GEN1_I2C_SDA_PC5,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+	PIN(GEN1_I2C_SCL_PC4,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP4_FS_PP4,            I2S3,       RSVD2,    DTV,          RSVD4),
+	PIN(DAP4_DIN_PP5,           I2S3,       RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP4_DOUT_PP6,          I2S3,       RSVD2,    DTV,          RSVD4),
+	PIN(DAP4_SCLK_PP7,          I2S3,       RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK3_OUT_PEE0,          EXTPERIPH3, RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK3_REQ_PEE1,          DEV3,       RSVD2,    RSVD3,        RSVD4),
+	PIN(GMI_WP_N_PC7,           RSVD1,      NAND,     GMI,          GMI_ALT),
+	PIN(GMI_IORDY_PI5,          SDMMC2,     RSVD2,    GMI,          TRACE),
+	PIN(GMI_WAIT_PI7,           SPI4,       NAND,     GMI,          DTV),
+	PIN(GMI_ADV_N_PK0,          RSVD1,      NAND,     GMI,          TRACE),
+	PIN(GMI_CLK_PK1,            SDMMC2,     NAND,     GMI,          TRACE),
+	PIN(GMI_CS0_N_PJ0,          RSVD1,      NAND,     GMI,          USB),
+	PIN(GMI_CS1_N_PJ2,          RSVD1,      NAND,     GMI,          SOC),
+	PIN(GMI_CS2_N_PK3,          SDMMC2,     NAND,     GMI,          TRACE),
+	PIN(GMI_CS3_N_PK4,          SDMMC2,     NAND,     GMI,          GMI_ALT),
+	PIN(GMI_CS4_N_PK2,          USB,        NAND,     GMI,          TRACE),
+	PIN(GMI_CS6_N_PI3,          NAND,       NAND_ALT, GMI,          SPI4),
+	PIN(GMI_CS7_N_PI6,          NAND,       NAND_ALT, GMI,          SDMMC2),
+	PIN(GMI_AD0_PG0,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD1_PG1,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD2_PG2,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD3_PG3,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD4_PG4,            RSVD1,      NAND,     GMI,          RSVD4),
+	PIN(GMI_AD5_PG5,            RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_AD6_PG6,            RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_AD7_PG7,            RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_AD8_PH0,            PWM0,       NAND,     GMI,          DTV),
+	PIN(GMI_AD9_PH1,            PWM1,       NAND,     GMI,          CLDVFS),
+	PIN(GMI_AD10_PH2,           PWM2,       NAND,     GMI,          CLDVFS),
+	PIN(GMI_AD11_PH3,           PWM3,       NAND,     GMI,          USB),
+	PIN(GMI_AD12_PH4,           SDMMC2,     NAND,     GMI,          RSVD4),
+	PIN(GMI_AD13_PH5,           SDMMC2,     NAND,     GMI,          RSVD4),
+	PIN(GMI_AD14_PH6,           SDMMC2,     NAND,     GMI,          DTV),
+	PIN(GMI_AD15_PH7,           SDMMC2,     NAND,     GMI,          DTV),
+	PIN(GMI_A16_PJ7,            UARTD,      TRACE,    GMI,          GMI_ALT),
+	PIN(GMI_A17_PB0,            UARTD,      RSVD2,    GMI,          TRACE),
+	PIN(GMI_A18_PB1,            UARTD,      RSVD2,    GMI,          TRACE),
+	PIN(GMI_A19_PK7,            UARTD,      SPI4,     GMI,          TRACE),
+	PIN(GMI_WR_N_PI0,           RSVD1,      NAND,     GMI,          SPI4),
+	PIN(GMI_OE_N_PI1,           RSVD1,      NAND,     GMI,          SOC),
+	PIN(GMI_DQS_P_PJ3,          SDMMC2,     NAND,     GMI,          TRACE),
+	PIN(GMI_RST_N_PI4,          NAND,       NAND_ALT, GMI,          RSVD4),
+	PIN(GEN2_I2C_SCL_PT5,       I2C2,       RSVD2,    GMI,          RSVD4),
+	PIN(GEN2_I2C_SDA_PT6,       I2C2,       RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_CLK_PCC4,        SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_CMD_PT7,         SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN(SDMMC4_DAT0_PAA0,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT1_PAA1,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT2_PAA2,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT3_PAA3,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT4_PAA4,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT5_PAA5,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT6_PAA6,       SDMMC4,     SPI3,     GMI,          RSVD4),
+	PIN(SDMMC4_DAT7_PAA7,       SDMMC4,     RSVD2,    GMI,          RSVD4),
+	PIN_RESERVED,
+	/* Offset 0x3284 */
+	PIN(CAM_MCLK_PCC0,          VI,         VI_ALT1,  VI_ALT3,      RSVD4),
+	PIN(PCC1,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PBB0,                   I2S4,       VI,       VI_ALT1,      VI_ALT3),
+	PIN(CAM_I2C_SCL_PBB1,       VGP1,       I2C3,     RSVD3,        RSVD4),
+	PIN(CAM_I2C_SDA_PBB2,       VGP2,       I2C3,     RSVD3,        RSVD4),
+	PIN(PBB3,                   VGP3,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB4,                   VGP4,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB5,                   VGP5,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB6,                   VGP6,       DISPLAYA, DISPLAYB,     RSVD4),
+	PIN(PBB7,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PCC2,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+	PIN(JTAG_RTCK,              RTCK,       RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_I2C_SCL_PZ6,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_I2C_SDA_PZ7,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW0_PR0,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW1_PR1,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW2_PR2,            KBC,        RSVD2,    RSVD3,        RSVD4),
+	PIN(KB_ROW3_PR3,            KBC,        DISPLAYA, RSVD3,        DISPLAYB),
+	PIN(KB_ROW4_PR4,            KBC,        DISPLAYA, SPI2,         DISPLAYB),
+	PIN(KB_ROW5_PR5,            KBC,        DISPLAYA, SPI2,         DISPLAYB),
+	PIN(KB_ROW6_PR6,            KBC,        DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+	PIN(KB_ROW7_PR7,            KBC,        RSVD2,    CLDVFS,       UARTA),
+	PIN(KB_ROW8_PS0,            KBC,        RSVD2,    CLDVFS,       UARTA),
+	PIN(KB_ROW9_PS1,            KBC,        RSVD2,    RSVD3,        UARTA),
+	PIN(KB_ROW10_PS2,           KBC,        RSVD2,    RSVD3,        UARTA),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x32fc */
+	PIN(KB_COL0_PQ0,            KBC,        USB,      SPI2,         EMC_DLL),
+	PIN(KB_COL1_PQ1,            KBC,        RSVD2,    SPI2,         EMC_DLL),
+	PIN(KB_COL2_PQ2,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_COL3_PQ3,            KBC,        DISPLAYA, PWM2,         UARTA),
+	PIN(KB_COL4_PQ4,            KBC,        OWR,      SDMMC3,       UARTA),
+	PIN(KB_COL5_PQ5,            KBC,        RSVD2,    SDMMC1,       RSVD4),
+	PIN(KB_COL6_PQ6,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(KB_COL7_PQ7,            KBC,        RSVD2,    SPI2,         RSVD4),
+	PIN(CLK_32K_OUT_PA0,        BLINK,      SOC,      RSVD3,        RSVD4),
+	PIN(SYS_CLK_REQ_PZ5,        SYSCLK,     RSVD2,    RSVD3,        RSVD4),
+	PIN(CORE_PWR_REQ,           PWRON,      RSVD2,    RSVD3,        RSVD4),
+	PIN(CPU_PWR_REQ,            CPU,        RSVD2,    RSVD3,        RSVD4),
+	PIN(PWR_INT_N,              PMI,        RSVD2,    RSVD3,        RSVD4),
+	PIN(CLK_32K_IN,             CLK,        RSVD2,    RSVD3,        RSVD4),
+	PIN(OWR,                    OWR,        RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP1_FS_PN0,            I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_DIN_PN1,           I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_DOUT_PN2,          I2S0,       HDA,      GMI,          RSVD4),
+	PIN(DAP1_SCLK_PN3,          I2S0,       HDA,      GMI,          RSVD4),
+	PIN(CLK1_REQ_PEE2,          DAP,        DAP1,     RSVD3,        RSVD4),
+	PIN(CLK1_OUT_PW4,           EXTPERIPH1, DAP2,     RSVD3,        RSVD4),
+	PIN(SPDIF_IN_PK6,           SPDIF,      USB,      RSVD3,        RSVD4),
+	PIN(SPDIF_OUT_PK5,          SPDIF,      RSVD2,    RSVD3,        RSVD4),
+	PIN(DAP2_FS_PA2,            I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DAP2_DIN_PA4,           I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DAP2_DOUT_PA5,          I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DAP2_SCLK_PA3,          I2S1,       HDA,      RSVD3,        RSVD4),
+	PIN(DVFS_PWM_PX0,           SPI6,       CLDVFS,   RSVD3,        RSVD4),
+	PIN(GPIO_X1_AUD_PX1,        SPI6,       RSVD2,    RSVD3,        RSVD4),
+	PIN(GPIO_X3_AUD_PX3,        SPI6,       SPI1,     RSVD3,        RSVD4),
+	PIN(DVFS_CLK_PX2,           SPI6,       CLDVFS,   RSVD3,        RSVD4),
+	PIN(GPIO_X4_AUD_PX4,        RSVD1,      SPI1,     SPI2,         DAP2),
+	PIN(GPIO_X5_AUD_PX5,        RSVD1,      SPI1,     SPI2,         RSVD4),
+	PIN(GPIO_X6_AUD_PX6,        SPI6,       SPI1,     SPI2,         RSVD4),
+	PIN(GPIO_X7_AUD_PX7,        RSVD1,      SPI1,     SPI2,         RSVD4),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x3390 */
+	PIN(SDMMC3_CLK_PA6,         SDMMC3,     RSVD2,    RSVD3,        SPI3),
+	PIN(SDMMC3_CMD_PA7,         SDMMC3,     PWM3,     UARTA,        SPI3),
+	PIN(SDMMC3_DAT0_PB7,        SDMMC3,     RSVD2,    RSVD3,        SPI3),
+	PIN(SDMMC3_DAT1_PB6,        SDMMC3,     PWM2,     UARTA,        SPI3),
+	PIN(SDMMC3_DAT2_PB5,        SDMMC3,     PWM1,     DISPLAYA,     SPI3),
+	PIN(SDMMC3_DAT3_PB4,        SDMMC3,     PWM0,     DISPLAYB,     SPI3),
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	PIN_RESERVED,
+	/* Offset 0x33e0 */
+	PIN(HDMI_CEC_PEE3,          CEC,        SDMMC3,   RSVD3,        SOC),
+	PIN(SDMMC1_WP_N_PV3,        SDMMC1,     CLK12,    SPI4,         UARTA),
+	PIN(SDMMC3_CD_N_PV2,        SDMMC3,     OWR,      RSVD3,        RSVD4),
+	PIN(GPIO_W2_AUD_PW2,        SPI6,       RSVD2,    SPI2,         I2C1),
+	PIN(GPIO_W3_AUD_PW3,        SPI6,       SPI1,     SPI2,         I2C1),
+	PIN(USB_VBUS_EN0_PN4,       USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(USB_VBUS_EN1_PN5,       USB,        RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+	PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+	PIN(GMI_CLK_LB,             SDMMC2,     NAND,     GMI,          RSVD4),
+	PIN(RESET_OUT_N,            RSVD1,      RSVD2,    RSVD3,        RESET_OUT_N),
+};
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;