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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-10-14 10:46:36 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-10-14 10:46:36 +0200 |
| commit | 13a3972585af60ec367d209cedbd3601e0c77467 (patch) | |
| tree | 4b3312669b3e501f6bc10b39d8c7bbf516f07aac /arch/arm/mach-tegra/tegra114 | |
| parent | 208bd51396fb606dbdcf45b064e6b372d7dd3e81 (diff) | |
| parent | 297faccca2235e359012118495b9b73451d54bb9 (diff) | |
Merge remote-tracking branch 'u-boot/master'
Diffstat (limited to 'arch/arm/mach-tegra/tegra114')
| -rw-r--r-- | arch/arm/mach-tegra/tegra114/clock.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 5e805a7baf..e6ef873c8d 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -629,6 +629,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz @@ -679,8 +684,8 @@ void arch_timer_init(void) struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; u32 freq, val; - freq = clock_get_rate(CLOCK_ID_OSC); - debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + freq = clock_get_rate(CLOCK_ID_CLK_M); + debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq); /* ARM CNTFRQ */ asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); |