Merge branch 'master' of git://git.denx.de/u-boot-tegra

3 files changed, 45 insertions, 21 deletions

diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index 25da771607..5ecadf705e 100644
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -249,6 +249,10 @@ static ulong carveout_size(void)
 {
 #ifdef CONFIG_ARM64
 	return SZ_512M;
+#elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
+	// BASE+SIZE might not == 4GB. If so, we want the carveout to cover
+	// from BASE to 4GB, not BASE to BASE+SIZE.
+	return (0 - CONFIG_ARMV7_SECURE_BASE);
 #else
 	return 0;
 #endif
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index d32d559f13..e45f0961b2 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -8,7 +8,7 @@
 
 #include <asm/io.h>
 #include <asm/types.h>
-#include <asm/arch/flow.h>
+
 #include <asm/arch/powergate.h>
 #include <asm/arch/tegra.h>
 
@@ -74,29 +74,11 @@ static int tegra_powergate_remove_clamping(enum tegra_powergate id)
 	return 0;
 }
 
-static void tegra_powergate_ram_repair(void)
-{
-#ifdef CONFIG_TEGRA124
-	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
-	/* Request RAM repair for cluster 0 and wait until complete */
-	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
-	while (!(readl(&flow->ram_repair) & RAM_REPAIR_STS))
-		;
-
-	/* Same for cluster 1 */
-	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
-	while (!(readl(&flow->ram_repair_cluster1) & RAM_REPAIR_STS))
-		;
-#endif
-}
-
 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
 				      enum periph_id periph)
 {
 	int err;
 
-	tegra_powergate_ram_repair();
 	reset_set_enable(periph, 1);
 
 	err = tegra_powergate_power_on(id);
diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c
index 204d6e9539..992c0beb04 100644
--- a/arch/arm/mach-tegra/tegra124/cpu.c
+++ b/arch/arm/mach-tegra/tegra124/cpu.c
@@ -104,6 +104,43 @@ static void remove_cpu_resets(void)
 	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
 }
 
+static void tegra124_ram_repair(void)
+{
+	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+	u32 ram_repair_timeout; /*usec*/
+	u32 val;
+
+	/*
+	 * Request the Flow Controller perform RAM repair whenever it turns on
+	 * a power rail that requires RAM repair.
+	 */
+	clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN);
+
+	/* Request SW trigerred RAM repair by setting req  bit */
+	/* cluster 0 */
+	setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
+	/* Wait for completion (status == 0) */
+	ram_repair_timeout = 500;
+	do {
+		udelay(1);
+		val = readl(&flow->ram_repair);
+	} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+	if (!ram_repair_timeout)
+		debug("Ram Repair cluster0 failed\n");
+
+	/* cluster 1 */
+	setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
+	/* Wait for completion (status == 0) */
+	ram_repair_timeout = 500;
+	do {
+		udelay(1);
+		val = readl(&flow->ram_repair_cluster1);
+	} while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
+
+	if (!ram_repair_timeout)
+		debug("Ram Repair cluster1 failed\n");
+}
+
 /**
  * Tegra124 requires some special clock initialization, including setting up
  * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
@@ -254,10 +291,11 @@ void start_cpu(u32 reset_vector)
 	       &pmc->pmc_pwrgate_timer_mult);
 
 	enable_cpu_power_rail();
+	powerup_cpus();
+	tegra124_ram_repair();
 	enable_cpu_clocks();
 	clock_enable_coresight(1);
-	remove_cpu_resets();
 	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-	powerup_cpus();
+	remove_cpu_resets();
 	debug("%s exit, should continue @ reset_vector\n", __func__);
 }