diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-08-10 16:08:40 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-08-11 17:49:14 +0900 |
| commit | 82d075e79fa509ffb8ecd8dd2dc216929d6e8289 (patch) | |
| tree | 0c503edf511c583c91d3fd2acacc6bd85ee76187 /arch/arm/mach-uniphier/arm32 | |
| parent | 0efbbc5c613b28614eb3323145b5d3eda4a33188 (diff) | |
ARM: uniphier: fix ROM boot mode for PH1-sLD3
Commit 4b50369fb535 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.
The idea here is to check the current page table to determine if
it is a straight map table. If not, adjust the outer cache register
base.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/arm32')
| -rw-r--r-- | arch/arm/mach-uniphier/arm32/lowlevel_init.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index 2be95058b3..b0c94ad01e 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -99,6 +99,11 @@ ENDPROC(enable_mmu) ENTRY(setup_init_ram) ldr r1, = SSCO_BASE + mrc p15, 0, r0, c2, c0, 0 @ TTBR0 + ldr r0, [r0, #0x400] @ entry for virtual address 0x100***** + bfc r0, #0, #20 + cmp r0, #0x50000000 @ is sLD3 page table? + biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1******* /* Touch to zero for the boot way */ 0: ldr r0, = 0x00408006 @ touch to zero with address range |