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authorMasahiro Yamada <yamada.masahiro@socionext.com>2019-07-10 20:07:40 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2019-07-10 22:42:00 +0900
commitd41b358fb331c2907f1f217686d38eeaf17eece4 (patch)
tree9d8ea673b2beca4fab63764e762f74c455021e62 /arch/arm/mach-uniphier/arm32
parentc3d8f1e8e92fd70abb912942300cf44fff9e9d86 (diff)
ARM: uniphier: de-couple SG macros into base address and offset
The SG_* macros represent the address of SoC-glue registers. For a planned new SoC, its base address will be changed. Turn the SG_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/arm32')
-rw-r--r--arch/arm/mach-uniphier/arm32/debug_ll.S16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S
index e56e1f679c..c155246ae8 100644
--- a/arch/arm/mach-uniphier/arm32/debug_ll.S
+++ b/arch/arm/mach-uniphier/arm32/debug_ll.S
@@ -22,7 +22,7 @@
#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
- ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
+ ldr \ra, =(SG_BASE + SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
ldr \rd, [\ra]
and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
@@ -30,7 +30,7 @@
.endm
ENTRY(debug_ll_init)
- ldr r0, =SG_REVISION
+ ldr r0, =(SG_BASE + SG_REVISION)
ldr r1, [r0]
and r1, r1, #SG_REVISION_TYPE_MASK
mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
@@ -40,7 +40,7 @@ ENTRY(debug_ll_init)
cmp r1, #0x26
bne ld4_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
@@ -59,7 +59,7 @@ ld4_end:
sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
- ldr r0, =SG_LOADPINCTRL
+ ldr r0, =(SG_BASE + SG_LOADPINCTRL)
mov r1, #1
str r1, [r0]
@@ -78,7 +78,7 @@ pro4_end:
cmp r1, #0x29
bne sld8_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
@@ -100,7 +100,7 @@ sld8_end:
sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
- ldr r0, =SG_LOADPINCTRL
+ ldr r0, =(SG_BASE + SG_LOADPINCTRL)
mov r1, #1
str r1, [r0]
@@ -119,7 +119,7 @@ pro5_end:
cmp r1, #0x2E
bne pxs2_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]
@@ -144,7 +144,7 @@ pxs2_end:
cmp r1, #0x2F
bne ld6b_end
- ldr r0, =SG_IECTRL
+ ldr r0, =(SG_BASE + SG_IECTRL)
ldr r1, [r0]
orr r1, r1, #1
str r1, [r0]