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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-04-21 14:43:18 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-04-24 09:54:08 +0900
commit9d0c2ceb35be7016977560a92fc67e3e704e5c9f (patch)
tree67f17e8bbc13a293b7d24f7789a3fb0692c1e284 /arch/arm/mach-uniphier/arm64/arm-cci500.c
parent881aa5a79a94a65500959428328f348a18d3d9fe (diff)
ARM: uniphier: add PH1-LD20 SoC support
This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/arm64/arm-cci500.c')
-rw-r--r--arch/arm/mach-uniphier/arm64/arm-cci500.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c
new file mode 100644
index 0000000000..607f96a58d
--- /dev/null
+++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c
@@ -0,0 +1,41 @@
+/*
+ * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define CCI500_BASE 0x5FD00000
+#define CCI500_SLAVE_OFFSET 0x1000
+
+#define CCI500_SNOOP_CTRL
+#define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
+#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
+
+void cci500_init(unsigned int nr_slaves)
+{
+ unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
+ int i;
+
+ for (i = 0; i < nr_slaves; i++) {
+ void __iomem *base;
+ u32 tmp;
+
+ base = map_sysmem(slave_base, SZ_4K);
+
+ tmp = readl(base);
+ tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
+ writel(tmp, base);
+
+ unmap_sysmem(base);
+
+ slave_base += CCI500_SLAVE_OFFSET;
+ }
+}