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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-01-15 14:59:03 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2017-01-17 09:00:40 +0900
commit78c627cf1f808d5ae9240809a81b71903bdf4fe2 (patch)
tree9193f6e6389c787efbea9b60ef9a567a09600a2e /arch/arm/mach-uniphier/clk/clk-dram-ld11.c
parenta314a245d14547df0a88e1ea568116fd7947daf4 (diff)
ARM: uniphier: split out UMC clock enable
The clock enable bits for UMC are more SoC-specific than for the other hardware blocks. Separate the UMC clocks and the other clocks for better code reuse across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk/clk-dram-ld11.c')
-rw-r--r--arch/arm/mach-uniphier/clk/clk-dram-ld11.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld11.c b/arch/arm/mach-uniphier/clk/clk-dram-ld11.c
new file mode 100644
index 0000000000..593e11a292
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-dram-ld11.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016-2017 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+void uniphier_ld11_dram_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL7);
+ tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
+ writel(tmp, SC_RSTCTRL7);
+
+ /* provide clocks */
+ tmp = readl(SC_CLKCTRL7);
+ tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
+ writel(tmp, SC_CLKCTRL7);
+}