diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-02-21 23:00:35 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-02-23 09:00:16 +0900 |
| commit | bc647958047cd03193e19cd8c08a6771fea828b7 (patch) | |
| tree | 35be69932e53e4c58260af58ae841a3d1a2523b6 /arch/arm/mach-uniphier/clk/pll-base-ld20.c | |
| parent | 9d35873161c98d3b9d92adacd7ee4c8fb1740068 (diff) | |
ARM: uniphier: set up charge pump current for MPLL of LD11 SoC
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk/pll-base-ld20.c')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-base-ld20.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index c66f083fae..697eb7aabf 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -18,6 +18,8 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) +#define SC_PLLCTRL3_REGI_SHIFT 16 +#define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ #define SC_VPLL27CTRL_WP BIT(0) @@ -77,6 +79,25 @@ int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) return 0; } +int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) +{ + void __iomem *base; + u32 tmp; + + base = ioremap(reg_base, SZ_16); + if (!base) + return -ENOMEM; + + tmp = readl(base + 8); /* SSCPLLCTRL */ + tmp &= ~SC_PLLCTRL3_REGI_MASK; + tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + writel(tmp, base + 8); + + iounmap(base); + + return 0; +} + int uniphier_ld20_vpll27_init(unsigned long reg_base) { void __iomem *base; |