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authorTom Rini <trini@konsulko.com>2019-07-11 18:08:44 -0400
committerTom Rini <trini@konsulko.com>2019-07-11 18:08:44 -0400
commit79b8d3c285f4f1c2ee4b27367f2ca3ecb76ed9ce (patch)
tree20571bc51871460b41b53c906881541e4ee2ce5c /arch/arm/mach-uniphier/clk/pll-pxs3.c
parent5acce685c9227b3d4b48f6fab6a33f6d74ca9c14 (diff)
parent2ce6b82d340cf1b1e5a43f1b5c8965d0067d5246 (diff)
Merge tag 'uniphier-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2019.10 - import DT updates from Linux - add UniPhier SPI controller driver - make U-Boot image for 64bit SoCs position independent - tidy up various init code for next generation SoCs - misc cleanups
Diffstat (limited to 'arch/arm/mach-uniphier/clk/pll-pxs3.c')
-rw-r--r--arch/arm/mach-uniphier/clk/pll-pxs3.c30
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c
index 5a1b1d25ac..278f530ea9 100644
--- a/arch/arm/mach-uniphier/clk/pll-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c
@@ -10,25 +10,25 @@
#include "pll.h"
/* PLL type: SSC */
-#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */
-#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */
-#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440)
-#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450)
-#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460)
-#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470)
-#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
-#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
-#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
-#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0)
+#define SC_CPLLCTRL 0x1400 /* CPU/ARM */
+#define SC_SPLLCTRL 0x1410 /* misc */
+#define SC_SPLL2CTRL 0x1420 /* DSP */
+#define SC_VPPLLCTRL 0x1430 /* VPE */
+#define SC_VGPLLCTRL 0x1440
+#define SC_DECPLLCTRL 0x1450
+#define SC_ENCPLLCTRL 0x1460
+#define SC_PXFPLLCTRL 0x1470
+#define SC_DPLL0CTRL 0x1480 /* DDR memory 0 */
+#define SC_DPLL1CTRL 0x1490 /* DDR memory 1 */
+#define SC_DPLL2CTRL 0x14a0 /* DDR memory 2 */
+#define SC_VSPLLCTRL 0x14c0
/* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
/* PLL type: DSPLL */
-#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540)
+#define SC_VPLL8KCTRL 0x1540
void uniphier_pxs3_pll_init(void)
{