diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-12-06 14:16:34 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-12-12 00:36:12 +0900 |
| commit | 7f8e75390b9c9b79748b2f87dd7ab45674323d58 (patch) | |
| tree | 1de9a77ffd87e77adb7948f604e182e113ddb07e /arch/arm/mach-uniphier/clk | |
| parent | f2ce50b2d076ccec56d33df71f77e6f3fd7a33f4 (diff) | |
ARM: uniphier: use FIELD_PREP for PLL settings
It is tedious to define both mask and bit-shift. <linux/bitfield.h>
provides a convenient way to get access to register fields with a
single shifted mask.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/clk')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/pll-base-ld20.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index c9b78b9e88..385f54dfc3 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/kernel.h> @@ -19,7 +20,6 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) -#define SC_PLLCTRL3_REGI_SHIFT 16 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ @@ -42,14 +42,16 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; - tmp |= DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, divn * 512) & - SC_PLLCTRL_SSC_DK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK, + DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, + divn * 512)); writel(tmp, base); tmp = readl(base + 4); tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; - tmp |= DIV_ROUND_CLOSEST(21431887UL * freq, divn * 512) & - SC_PLLCTRL2_SSC_JK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK, + DIV_ROUND_CLOSEST(21431887UL * freq, + divn * 512)); writel(tmp, base + 4); udelay(50); @@ -93,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; - tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); writel(tmp, base + 8); iounmap(base); |