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authorMasahiro Yamada <yamada.masahiro@socionext.com>2019-07-10 20:07:40 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2019-07-10 22:42:00 +0900
commitd41b358fb331c2907f1f217686d38eeaf17eece4 (patch)
tree9d8ea673b2beca4fab63764e762f74c455021e62 /arch/arm/mach-uniphier/debug-uart/debug-uart.c
parentc3d8f1e8e92fd70abb912942300cf44fff9e9d86 (diff)
ARM: uniphier: de-couple SG macros into base address and offset
The SG_* macros represent the address of SoC-glue registers. For a planned new SoC, its base address will be changed. Turn the SG_* macros into the offset from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/debug-uart/debug-uart.c')
-rw-r--r--arch/arm/mach-uniphier/debug-uart/debug-uart.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
index bc96b2e7be..a70ce59acc 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
@@ -32,7 +32,8 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval,
unsigned int mux_bits, unsigned int reg_stride)
{
unsigned int shift = pin * mux_bits % 32;
- unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+ void __iomem *reg = sg_base + SG_PINCTRL_BASE +
+ pin * mux_bits / 32 * reg_stride;
u32 mask = (1U << mux_bits) - 1;
u32 tmp;
@@ -45,7 +46,7 @@ void sg_set_pinsel(unsigned int pin, unsigned int muxval,
void sg_set_iectrl(unsigned int pin)
{
unsigned int bit = pin % 32;
- unsigned long reg = SG_IECTRL + pin / 32 * 4;
+ void __iomem *reg = sg_base + SG_IECTRL + pin / 32 * 4;
u32 tmp;
tmp = readl(reg);