diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-26 14:21:38 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-29 03:50:16 +0900 |
| commit | 00dd3f6ab068276f8baa409e9317fbf466187a34 (patch) | |
| tree | bdc2a6417b93553f6c641d77bc7e5fd7547364e8 /arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | |
| parent | 94b756f3318b5dea3c1aefa670f43ae85d780144 (diff) | |
ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings
These settings were used only for the PH1-sLD3 and older SoCs. The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram/umc-ph1-pro4.c')
| -rw-r--r-- | arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index ff988e3540..c28492c4f1 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -20,7 +20,6 @@ enum dram_size { DRAM_SZ_NR, }; -static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f}; static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617}; static void umc_start_ssif(void __iomem *ssif_base) @@ -88,13 +87,6 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x66bb0f17, dramcont + UMC_CMDCTLA); writel(0x18c6aa44, dramcont + UMC_CMDCTLB); - writel(0x5101387f, dramcont + UMC_INITCTLA); - writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB); - writel(0x00ff00ff, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000298, dramcont + UMC_DRMMR2); - writel(0x00000000, dramcont + UMC_DRMMR3); writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA); writel(0x00ff0008, dramcont + UMC_SPCCTLB); writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); |