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authorMasahiro Yamada <yamada.masahiro@socionext.com>2019-07-10 20:07:45 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2019-07-10 22:42:05 +0900
commit34e29f7d94aa0243793081751ea0eeae598a0273 (patch)
tree7bc9a99ef4ff8f6f3abc3b8061178920c54a02d3 /arch/arm/mach-uniphier/dram_init.c
parentdf72534121b7e593f2a8043ad1c0c86bae0aa75b (diff)
ARM: uniphier: make mem_map run-time configurable
Currently, mem_map is hard-coded, and it worked well until the last SoC. For a planned new SoC, the addresses of peripherals and DRAM will be changed. Set it up run-time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/dram_init.c')
-rw-r--r--arch/arm/mach-uniphier/dram_init.c24
1 files changed, 20 insertions, 4 deletions
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index ab4aa93f42..970fa09ef0 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -13,6 +13,7 @@
#include <linux/sizes.h>
#include <asm/global_data.h>
+#include "init.h"
#include "sg-regs.h"
#include "soc-info.h"
@@ -271,6 +272,8 @@ int dram_init(void)
int dram_init_banksize(void)
{
struct uniphier_dram_map dram_map[3] = {};
+ unsigned long base, top;
+ bool valid_bank_found = false;
int ret, i;
ret = uniphier_dram_map_get(dram_map);
@@ -278,12 +281,25 @@ int dram_init_banksize(void)
return ret;
for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
- if (i >= ARRAY_SIZE(gd->bd->bi_dram))
- break;
+ if (i < ARRAY_SIZE(gd->bd->bi_dram)) {
+ gd->bd->bi_dram[i].start = dram_map[i].base;
+ gd->bd->bi_dram[i].size = dram_map[i].size;
+ }
+
+ if (!dram_map[i].size)
+ continue;
- gd->bd->bi_dram[i].start = dram_map[i].base;
- gd->bd->bi_dram[i].size = dram_map[i].size;
+ if (!valid_bank_found)
+ base = dram_map[i].base;
+ top = dram_map[i].base + dram_map[i].size;
+ valid_bank_found = true;
}
+ if (!valid_bank_found)
+ return -EINVAL;
+
+ /* map all the DRAM regions */
+ uniphier_mem_map_init(base, top - base);
+
return 0;
}