ARM: uniphier: refactor MEMCONF init code

Currently, memconf-sld3.c and memconf-pxs2.c duplicate the code.

There are 3 patterns in terms of MEMCONF init:
  - DRAM 2 channels: LD4, sLD8, Pro4, Pro5, LD11
  - DRAM 3 channels: sLD3
  - DRAM 3 channels (Ch2 is disable by MEMCONF[21]): Pxs2, LD20

All of them can be moved into a single file by a little more
refactoring.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 0 insertions, 107 deletions

diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
deleted file mode 100644
index e607ac9c3b..0000000000
--- a/arch/arm/mach-uniphier/memconf/memconf.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2016      Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../init.h"
-#include "../sg-regs.h"
-
-int memconf_init(const struct uniphier_board_data *bd)
-{
-	u32 tmp;
-	unsigned long size_per_word;
-
-	tmp = readl(SG_MEMCONF);
-
-	tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
-
-	switch (bd->dram_ch[0].width) {
-	case 16:
-		tmp |= SG_MEMCONF_CH0_NUM_1;
-		size_per_word = bd->dram_ch[0].size;
-		break;
-	case 32:
-		tmp |= SG_MEMCONF_CH0_NUM_2;
-		size_per_word = bd->dram_ch[0].size >> 1;
-		break;
-	default:
-		pr_err("error: unsupported DRAM Ch0 width\n");
-		return -EINVAL;
-	}
-
-	/* Set DDR size */
-	switch (size_per_word) {
-	case SZ_64M:
-		tmp |= SG_MEMCONF_CH0_SZ_64M;
-		break;
-	case SZ_128M:
-		tmp |= SG_MEMCONF_CH0_SZ_128M;
-		break;
-	case SZ_256M:
-		tmp |= SG_MEMCONF_CH0_SZ_256M;
-		break;
-	case SZ_512M:
-		tmp |= SG_MEMCONF_CH0_SZ_512M;
-		break;
-	case SZ_1G:
-		tmp |= SG_MEMCONF_CH0_SZ_1G;
-		break;
-	default:
-		pr_err("error: unsupported DRAM Ch0 size\n");
-		return -EINVAL;
-	}
-
-	tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
-
-	switch (bd->dram_ch[1].width) {
-	case 16:
-		tmp |= SG_MEMCONF_CH1_NUM_1;
-		size_per_word = bd->dram_ch[1].size;
-		break;
-	case 32:
-		tmp |= SG_MEMCONF_CH1_NUM_2;
-		size_per_word = bd->dram_ch[1].size >> 1;
-		break;
-	default:
-		pr_err("error: unsupported DRAM Ch1 width\n");
-		return -EINVAL;
-	}
-
-	switch (size_per_word) {
-	case SZ_64M:
-		tmp |= SG_MEMCONF_CH1_SZ_64M;
-		break;
-	case SZ_128M:
-		tmp |= SG_MEMCONF_CH1_SZ_128M;
-		break;
-	case SZ_256M:
-		tmp |= SG_MEMCONF_CH1_SZ_256M;
-		break;
-	case SZ_512M:
-		tmp |= SG_MEMCONF_CH1_SZ_512M;
-		break;
-	case SZ_1G:
-		tmp |= SG_MEMCONF_CH1_SZ_1G;
-		break;
-	default:
-		pr_err("error: unsupported DRAM Ch1 size\n");
-		return -EINVAL;
-	}
-
-	if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
-		tmp |= SG_MEMCONF_SPARSEMEM;
-	else
-		tmp &= ~SG_MEMCONF_SPARSEMEM;
-
-	writel(tmp, SG_MEMCONF);
-
-	return 0;
-}