diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-11 20:17:47 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-09-25 00:27:53 +0900 |
| commit | d5ed8c5727f6985505ceb6e8640528e7e08e9670 (patch) | |
| tree | 8730893f54c4f2f676281a47694efb3517753ee8 /arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | |
| parent | 4ef542efd54e24c523506df174c4d1978800ef9c (diff) | |
ARM: uniphier: change the external bus address mapping
In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
0x00000000 - 0x0fffffff
0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.
In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.
Going forward, use the latter for the external bus.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-uniphier/ph1-sld3/sbc_init.c')
| -rw-r--r-- | arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c index d66f89ea51..bafab4b0e6 100644 --- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c @@ -24,18 +24,18 @@ void sbc_init(void) if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x03efffff: memory bank (31MB) - * 0x03f00000-0x03ffffff: peripherals (1MB) + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); |