diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-18 16:41:44 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-03-24 01:45:18 +0900 |
| commit | 5d0607c58c02204c7ec02f0f4d6bd268929961ee (patch) | |
| tree | 24aecfd06a5712f8438a3b5f68ad354372156689 /arch/arm/mach-uniphier/sbc/sbc-pxs2.c | |
| parent | ea65c98050f0f13f933119e1d073c8a138481ee4 (diff) | |
ARM: uniphier: refactor SBC init code
There is a bunch of duplication in the System Bus Controller init
code. Roughly, there are two types in the SBC mode: Adress/Data
Multiplex Mode and Save Pins Mode. Consolidate per-SoC functions
into the two, plus per-SoC optional init code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/sbc/sbc-pxs2.c')
| -rw-r--r-- | arch/arm/mach-uniphier/sbc/sbc-pxs2.c | 34 |
1 files changed, 2 insertions, 32 deletions
diff --git a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c index 0d9ffe153f..acbf4c53fb 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-pxs2.c +++ b/arch/arm/mach-uniphier/sbc/sbc-pxs2.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,43 +7,13 @@ #include <linux/io.h> #include "../init.h" -#include "../sg-regs.h" #include "sbc-regs.h" -int proxstream2_sbc_init(const struct uniphier_board_data *bd) +int uniphier_pxs2_sbc_init(const struct uniphier_board_data *bd) { /* necessary for ROM boot ?? */ /* system bus output enable */ writel(0x17, PC0CTRL); - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } - return 0; } |