diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2019-09-11 09:39:59 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2019-10-08 09:11:14 +0200 |
| commit | 3899ebdd88f08929fd4568ce1c924176e6aa4365 (patch) | |
| tree | 593c21a0da4997b1a3960090ad19f9914778a507 /arch/arm/mach-versal | |
| parent | aef149e9dd3d8a99840b0a7e5af06565cde3ad74 (diff) | |
arm64: zynqmp: Provide a Kconfig option to disable OCM and TCM MMU mapping
This patch provides an option to enable/disable OCM and TCM memory into MMU
table with corresponding memory attributes.
The same change was done for ZynqMP by commit 189bec47ab1f
("arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-versal')
| -rw-r--r-- | arch/arm/mach-versal/Kconfig | 7 | ||||
| -rw-r--r-- | arch/arm/mach-versal/cpu.c | 25 |
2 files changed, 24 insertions, 8 deletions
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 26d1756371..06a0352924 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -54,4 +54,11 @@ config SYS_MEM_RSVD_FOR_MMU MMU table than the one which will be allocated during relocation. +config DEFINE_TCM_OCM_MMAP + bool "Define TCM and OCM memory in MMU Table" + default y if MP + help + This option if enabled defines the TCM and OCM memory and its + memory attributes in MMU table entry. + endif diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index dc6a9205be..f0d047d323 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -12,12 +12,18 @@ DECLARE_GLOBAL_DATA_PTR; -#define VERSAL_MEM_MAP_USED 6 +#define VERSAL_MEM_MAP_USED 5 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) +#define TCM_MAP 1 +#else +#define TCM_MAP 0 +#endif + /* +1 is end of list which needs to be empty */ -#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + 1) +#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1) static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { { @@ -35,12 +41,6 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0xffe00000UL, - .phys = 0xffe00000UL, - .size = 0x00200000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { .virt = 0x400000000UL, .phys = 0x400000000UL, .size = 0x200000000UL, @@ -67,6 +67,15 @@ void mem_map_fill(void) { int banks = VERSAL_MEM_MAP_USED; +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) + versal_mem_map[banks].virt = 0xffe00000UL; + versal_mem_map[banks].phys = 0xffe00000UL; + versal_mem_map[banks].size = 0x00200000UL; + versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; +#endif + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { /* Zero size means no more DDR that's this is end */ if (!gd->bd->bi_dram[i].size) |