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author | Michal Simek <michal.simek@xilinx.com> | 2020-03-18 13:45:21 +0100 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2020-04-06 12:52:45 +0200 |
commit | 98da86681e5158195314fd5df4ff605d3bb63d75 (patch) | |
tree | b11673f68aab900900c598d8dfbbe27a004e27a9 /arch/arm/mach-versal | |
parent | b8c3d3f45fb3cfd164ecec2f34ab7fcb5985bcfc (diff) |
arm64: versal: Disable DDR cache mapping if DDR is not enabled
Similar change was done in past by commit 3b644a3c2f69
("arm64: zynqmp: Provide a config to not map DDR region in MMU table").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/mach-versal')
-rw-r--r-- | arch/arm/mach-versal/Kconfig | 6 | ||||
-rw-r--r-- | arch/arm/mach-versal/cpu.c | 9 |
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index a08e5ae414..e1d66e8d32 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -56,4 +56,10 @@ config DEFINE_TCM_OCM_MMAP This option if enabled defines the TCM and OCM memory and its memory attributes in MMU table entry. +config VERSAL_NO_DDR + bool "Disable DDR MMU mapping" + help + This option configures MMU with no DDR to avoid speculative + access to DDR memory where DDR is not present. + endif diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 6ee6cd43ec..829a6c1b3e 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -81,6 +81,15 @@ void mem_map_fill(void) if (!gd->bd->bi_dram[i].size) break; +#if defined(CONFIG_VERSAL_NO_DDR) + if (gd->bd->bi_dram[i].start < 0x80000000UL || + gd->bd->bi_dram[i].start > 0x100000000UL) { + printf("Ignore caches over %llx/%llx\n", + gd->bd->bi_dram[i].start, + gd->bd->bi_dram[i].size); + continue; + } +#endif versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; versal_mem_map[banks].size = gd->bd->bi_dram[i].size; |