diff options
| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-11-21 11:36:48 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-12-05 08:31:45 -0800 |
| commit | 02fb2761576be8096ebf1b3f961a2cdb21b422ae (patch) | |
| tree | 70cd556e7498ef63f2d51519958cfc2994c73950 /arch/arm | |
| parent | 5a17b8b5dab8973089b7400d05f8503d56f29370 (diff) | |
fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d6ee54642d..ffbbd729d4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -26,6 +26,9 @@ #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif +#ifdef CONFIG_SYS_FSL_DDR +#include <fsl_ddr.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -403,7 +406,9 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 erratum_a009635(); #endif - +#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) + erratum_a009942_check_cpo(); +#endif #ifdef CONFIG_MP #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) /* Check the psci version to determine if the psci is supported */ |