diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2017-05-17 11:44:44 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2017-06-07 07:29:21 -0600 |
| commit | 077eb3151442462cae020ab7254cc3e73407e5c8 (patch) | |
| tree | 2e8a15044da5e1b7501a5bec054cf43ed76b0936 /arch/arm | |
| parent | 6f0c12371302b375c0fe87c0bcb5b19de03e9d38 (diff) | |
rockchip: pinctrl: rk3328: do not set io routing
In rk3328, some function pin may have more than one choice, and muxed
with more than one IO, for example, the UART2 controller IO,
TX and RX, have 3 choice(setting in com_iomux):
- M0 which mux with GPIO1A0/GPIO1A1
- M1 which mux with GPIO2A0/GPIO2A1
- usb2phy which mux with USB2.0 DP/DM pin.
We should not decide which group to use in pinctrl driver,
for it may be different in different board, it should goes to board
file, and the pinctrl file should setting correct iomux depends on
the com_iomux value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h index 40a4de0db6..f0a0781d8d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -228,21 +228,21 @@ enum { GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, /* COM_IOMUX */ - UART2_IOMUX_SEL_SHIFT = 0, - UART2_IOMUX_SEL_MASK = 3 << UART2_IOMUX_SEL_SHIFT, - UART2_IOMUX_SEL_M0 = 0, - UART2_IOMUX_SEL_M1, - - SPI_IOMUX_SEL_SHIFT = 4, - SPI_IOMUX_SEL_MASK = 3 << SPI_IOMUX_SEL_SHIFT, - SPI_IOMUX_SEL_M0 = 0, - SPI_IOMUX_SEL_M1, - SPI_IOMUX_SEL_M2, - - CARD_IOMUX_SEL_SHIFT = 7, - CARD_IOMUX_SEL_MASK = 1 << CARD_IOMUX_SEL_SHIFT, - CARD_IOMUX_SEL_M0 = 0, - CARD_IOMUX_SEL_M1, + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + + IOMUX_SEL_SPI_SHIFT = 4, + IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, + IOMUX_SEL_SPI_M0 = 0, + IOMUX_SEL_SPI_M1, + IOMUX_SEL_SPI_M2, + + IOMUX_SEL_SDMMC_SHIFT = 7, + IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, + IOMUX_SEL_SDMMC_M0 = 0, + IOMUX_SEL_SDMMC_M1, }; #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ |