diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2016-02-11 15:47:18 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-02-24 18:42:50 -0500 |
| commit | 09959ba3c5f0f56bed4b3ab008f9e159e1b28cd9 (patch) | |
| tree | 3cc5482daf511dc0c000c9002d62c4a7ae2365fe /arch/arm | |
| parent | 14cec061139a8fb0461d8748d14a2dbcf8a56f2e (diff) | |
gpio: stm32_gpio: move base addresses to the soc file
Base addresses for GPIOs could be different for different socs, this
patch moves the base addresses from driver to the soc specific location.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f1/stm32.h | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f4/stm32.h | 10 |
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h index 4094a75393..1af73c5428 100644 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ b/arch/arm/include/asm/arch-stm32f1/stm32.h @@ -24,6 +24,14 @@ #define STM32_BUS_MASK 0xFFFF0000 +#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) +#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) +#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) +#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) +#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) +#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) +#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) + /* * Register maps */ diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 6b64d0361b..7d6331b6b2 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -23,6 +23,16 @@ #define STM32_BUS_MASK 0xFFFF0000 +#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) +#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) +#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) +#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) +#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) +#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) +#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) +#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) +#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) + /* * Register maps */ |