diff options
author | Tien Fong Chee <tien.fong.chee@intel.com> | 2019-05-07 17:42:30 +0800 |
---|---|---|
committer | Marek Vasut <marex@denx.de> | 2019-05-10 22:48:11 +0200 |
commit | 1085bb3cbaf8321fdc8d0eaa367192433bd51d44 (patch) | |
tree | 099e967755262df7e02f0ce5a23172cfb2373f93 /arch/arm | |
parent | f61d52926086bf56c870f06ba5e88bdb41ac246e (diff) |
spl: socfpga: Implement fpga bitstream loading with socfpga loadfs
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-socfpga/spl_a10.c | 31 |
2 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h index c5f67714aa..62249b3695 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -126,6 +126,7 @@ int fpgamgr_program_finish(void); int is_fpgamgr_user_mode(void); int fpgamgr_wait_early_user_mode(void); const char *get_fpga_filename(void); +int is_fpgamgr_early_user_mode(void); int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, u32 offset); void fpgamgr_program(const void *buf, size_t bsize, u32 offset); diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c8e73d47c0..b466307f98 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com> */ #include <common.h> @@ -23,6 +23,11 @@ #include <fdtdec.h> #include <watchdog.h> #include <asm/arch/pinmux.h> +#include <asm/arch/fpga_manager.h> +#include <mmc.h> +#include <memalign.h> + +#define FPGA_BUFSIZ 16 * 1024 DECLARE_GLOBAL_DATA_PTR; @@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device) void spl_board_init(void) { + ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ); + /* enable console uart printing */ preloader_console_init(); WATCHDOG_RESET(); arch_early_init_r(); + + /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ + if (is_fpgamgr_user_mode()) { + int ret = config_pins(gd->fdt_blob, "shared"); + + if (ret) + return; + + ret = config_pins(gd->fdt_blob, "fpga"); + if (ret) + return; + } else if (!is_fpgamgr_early_user_mode()) { + /* Program IOSSM(early IO release) or full FPGA */ + fpgamgr_program(buf, FPGA_BUFSIZ, 0); + } + + /* If the IOSSM/full FPGA is already loaded, start DDR */ + if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) + ddr_calibration_sequence(); + + if (!is_fpgamgr_user_mode()) + fpgamgr_program(buf, FPGA_BUFSIZ, 0); } void board_init_f(ulong dummy) |