Merge branch 'master' of git://git.denx.de/u-boot-atmel

5 files changed, 221 insertions, 14 deletions

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c33364758b..9426302b38 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -74,6 +74,7 @@ config TARGET_AT91SAM9X5EK
 config TARGET_SAMA5D2_XPLAINED
 	bool "SAMA5D2 Xplained board"
 	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_SAMA5D3_XPLAINED
 	bool "SAMA5D3 Xplained board"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 5b89617623..abd1d13da7 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
+obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index c6c8dda803..d37d9082cd 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -2,31 +2,69 @@
  * Copyright (C) 2013 Atmel Corporation
  *		      Bo Shen <voice.shen@atmel.com>
  *
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Wenyou Yang <wenyou.yang@atmel.com>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __ATMEL_MPDDRC_H__
 #define __ATMEL_MPDDRC_H__
 
-/*
- * Only define the needed register in mpddr
- * If other register needed, will add them later
- */
-struct atmel_mpddr {
+struct atmel_mpddrc_config {
 	u32 mr;
 	u32 rtr;
 	u32 cr;
 	u32 tpr0;
 	u32 tpr1;
 	u32 tpr2;
-	u32 reserved[2];
 	u32 md;
 };
 
+/*
+ * Only define the needed register in mpddr
+ * If other register needed, will add them later
+ */
+struct atmel_mpddr {
+	u32 mr;			/* 0x00: Mode Register */
+	u32 rtr;		/* 0x04: Refresh Timer Register */
+	u32 cr;			/* 0x08: Configuration Register */
+	u32 tpr0;		/* 0x0c: Timing Parameter 0 Register */
+	u32 tpr1;		/* 0x10: Timing Parameter 1 Register */
+	u32 tpr2;		/* 0x14: Timing Parameter 2 Register */
+	u32 reserved;		/* 0x18: Reserved */
+	u32 lpr;		/* 0x1c: Low-power Register */
+	u32 md;			/* 0x20: Memory Device Register */
+	u32 reserved1;		/* 0x24: Reserved */
+	u32 lpddr23_lpr;	/* 0x28: LPDDR2-LPDDR3 Low-power Register*/
+	u32 cal_mr4;		/* 0x2c: Calibration and MR4 Register */
+	u32 tim_cal;		/* 0x30: Timing Calibration Register */
+	u32 io_calibr;		/* 0x34: IO Calibration */
+	u32 ocms;		/* 0x38: OCMS Register */
+	u32 ocms_key1;		/* 0x3c: OCMS KEY1 Register */
+	u32 ocms_key2;		/* 0x40: OCMS KEY2 Register */
+	u32 conf_arbiter;	/* 0x44: Configuration Arbiter Register */
+	u32 timeout;		/* 0x48: Timeout Port 0/1/2/3 Register */
+	u32 req_port0123;	/* 0x4c: Request Port 0/1/2/3 Register */
+	u32 req_port4567;	/* 0x50: Request Port 4/5/6/7 Register */
+	u32 bdw_port0123;	/* 0x54: Bandwidth Port 0/1/2/3 Register */
+	u32 bdw_port4567;	/* 0x58: Bandwidth Port 4/5/6/7 Register */
+	u32 rd_data_path;	/* 0x5c: Read Datapath Register */
+	u32 reserved2[33];
+	u32 wpmr;		/* 0xe4: Write Protection Mode Register */
+	u32 wpsr;		/* 0xe8: Write Protection Status Register */
+	u32 reserved3[4];
+	u32 version;		/* 0xfc: IP version */
+};
+
 
 int ddr2_init(const unsigned int base,
 	      const unsigned int ram_address,
-	      const struct atmel_mpddr *mpddr);
+	      const struct atmel_mpddrc_config *mpddr_value);
+
+int ddr3_init(const unsigned int base,
+	      const unsigned int ram_address,
+	      const struct atmel_mpddrc_config *mpddr_value);
 
 /* Bit field in mode register */
 #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD		0x0
@@ -110,9 +148,51 @@ int ddr2_init(const unsigned int base,
 
 /* Bit field in Memory Device Register */
 #define ATMEL_MPDDRC_MD_LPDDR_SDRAM	0x3
+#define ATMEL_MPDDRC_MD_DDR3_SDRAM	0x4
+#define ATMEL_MPDDRC_MD_LPDDR3_SDRAM	0x5
 #define ATMEL_MPDDRC_MD_DDR2_SDRAM	0x6
 #define ATMEL_MPDDRC_MD_DBW_MASK	(0x1 << 4)
 #define ATMEL_MPDDRC_MD_DBW_32_BITS	(0x0 << 4)
 #define ATMEL_MPDDRC_MD_DBW_16_BITS	(0x1 << 4)
 
+/* Bit field in I/O Calibration Register */
+#define ATMEL_MPDDRC_IO_CALIBR_RDIV		0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3	0x1
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40	0x2
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48	0x3
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60	0x4
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80	0x6
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120	0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35	0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43	0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52	0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70	0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_105	0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37	0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44	0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55	0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73	0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110	0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37	0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44	0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55	0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73	0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110	0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_TZQIO		0x7f
+#define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x)	(((x) & 0x7f) << 8)
+
+#define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB		(0x1 << 4)
+
+/* Bit field in Read Data Path Register */
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING	0x3
+#define ATMEL_MPDDRC_RD_DATA_PATH_NO_SHIFT		0x0
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE	0x1
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE	0x2
+#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE	0x3
+
 #endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index c85571c999..dd5a2a7523 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -106,6 +106,7 @@
 #define ATMEL_BASE_MPDDRC	0xf000c000
 #define ATMEL_BASE_XDMAC0	0xf0010000
 #define ATMEL_BASE_PMC		0xf0014000
+#define ATMEL_BASE_MATRIX0	0xf0018000
 #define ATMEL_BASE_QSPI0	0xf0020000
 #define ATMEL_BASE_QSPI1	0xf0024000
 #define ATMEL_BASE_SPI0		0xf8000000
@@ -117,6 +118,7 @@
 #define ATMEL_BASE_UART1	0xf8020000
 #define ATMEL_BASE_UART2	0xf8024000
 #define ATMEL_BASE_TWI0		0xf8028000
+#define ATMEL_BASE_SFR		0xf8030000
 #define ATMEL_BASE_SYSC		0xf8048000
 #define ATMEL_BASE_SPI1		0xfc000000
 #define ATMEL_BASE_UART3	0xfc008000
@@ -125,6 +127,7 @@
 #define ATMEL_BASE_UDPHS	0xfc02c000
 
 #define ATMEL_BASE_PIOA		0xfc038000
+#define ATMEL_BASE_MATRIX1	0xfc03c000
 
 #define ATMEL_CHIPID_CIDR	0xfc069000
 #define ATMEL_CHIPID_EXID	0xfc069004
@@ -171,6 +174,35 @@
 #define CPU_HAS_PCR
 #define CPU_HAS_H32MXDIV
 
+/* AICREDIR Unlock Key */
+#define ATMEL_SFR_AICREDIR_KEY		0xB6D81C4D
+
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE	0	/* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE	1	/* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_DDRC_PORT0		2	/* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1		3	/* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2		4	/* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3		5	/* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4		6	/* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5		7	/* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6		8	/* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7		9	/* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM		10	/* Internal SRAM 128K */
+#define H64MX_SLAVE_CACHE_L2		11	/* Internal SRAM 128K(L2) */
+#define H64MX_SLAVE_QSPI0		12	/* QSPI0 */
+#define H64MX_SLAVE_QSPI1		13	/* QSPI1 */
+#define H64MX_SLAVE_AESB		14	/* AESB */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE	0	/* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0	1	/* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1	2	/* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI			3	/* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD		3	/* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM		4	/* NFC SRAM */
+#define H32MX_SLAVE_USB			5	/* USB Device & Host */
+
 /* SAMA5D2 series chip id definitions */
 #define ARCH_ID_SAMA5D2		0x8a5c08c0
 #define ARCH_EXID_SAMA5D21CU	0x0000005a
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 47e6e5a3cd..16e089c3a0 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -2,6 +2,9 @@
  * Copyright (C) 2013 Atmel Corporation
  *		      Bo Shen <voice.shen@atmel.com>
  *
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Wenyou Yang <wenyou.yang@atmel.com>
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
@@ -9,6 +12,8 @@
 #include <asm/io.h>
 #include <asm/arch/atmel_mpddrc.h>
 
+#define SAMA5D3_MPDDRC_VERSION		0x140
+
 static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
 	      int mode,
 	      u32 ram_address)
@@ -17,20 +22,22 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
 	writel(0, ram_address);
 }
 
-static int ddr2_decodtype_is_seq(u32 cr)
+static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr)
 {
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
-	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
+	u16 version = readl(&mpddr->version) & 0xffff;
+
+	if ((version >= SAMA5D3_MPDDRC_VERSION) &&
+	    (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
 		return 0;
-#endif
+
 	return 1;
 }
 
 
 int ddr2_init(const unsigned int base,
 	      const unsigned int ram_address,
-	      const struct atmel_mpddr *mpddr_value)
+	      const struct atmel_mpddrc_config *mpddr_value)
 {
 	const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
 
@@ -38,7 +45,7 @@ int ddr2_init(const unsigned int base,
 
 	/* Compute bank offset according to NC in configuration register */
 	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
-	if (ddr2_decodtype_is_seq(mpddr_value->cr))
+	if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
 		ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
 
 	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
@@ -135,3 +142,89 @@ int ddr2_init(const unsigned int base,
 
 	return 0;
 }
+
+int ddr3_init(const unsigned int base,
+	      const unsigned int ram_address,
+	      const struct atmel_mpddrc_config *mpddr_value)
+{
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
+	u32 ba_off;
+
+	/* Compute bank offset according to NC in configuration register */
+	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
+	if (ddr2_decodtype_is_seq(base, mpddr_value->cr))
+		ba_off += ((mpddr_value->cr &
+			   ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+
+	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
+
+	/* Program the memory device type */
+	writel(mpddr_value->md, &mpddr->md);
+
+	/*
+	 * Program features of the DDR3-SDRAM device and timing parameters
+	 */
+	writel(mpddr_value->cr, &mpddr->cr);
+
+	writel(mpddr_value->tpr0, &mpddr->tpr0);
+	writel(mpddr_value->tpr1, &mpddr->tpr1);
+	writel(mpddr_value->tpr2, &mpddr->tpr2);
+
+	/* A NOP command is issued to the DDR3-SRAM */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/* A pause of at least 500us must be observed before a single toggle. */
+	udelay(500);
+
+	/* A NOP command is issued to the DDR3-SDRAM */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/*
+	 * An Extended Mode Register Set (EMRS2) cycle is issued to choose
+	 * between commercial or high temperature operations.
+	 */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x2 << ba_off));
+	/*
+	 * Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
+	 * the Extended Mode Register to 0.
+	 */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x3 << ba_off));
+	/*
+	 * An Extended Mode Register Set (EMRS1) cycle is issued to disable and
+	 * to program O.D.S. (Output Driver Strength).
+	 */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	/*
+	 * Write a one to the DLL bit (enable DLL reset) in the MPDDRC
+	 * Configuration Register.
+	 */
+
+	/* A Mode Register Set (MRS) cycle is issued to reset DLL. */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+	udelay(50);
+
+	/*
+	 * A Calibration command (MRS) is issued to calibrate RTT and RON
+	 * values for the Process Voltage Temperature (PVT).
+	 */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address);
+
+	/* A Normal Mode command is provided. */
+	atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
+
+	/* Perform a write access to any DDR3-SDRAM address. */
+	writel(0, ram_address);
+
+	/*
+	 * Write the refresh rate into the COUNT field in the MPDDRC
+	 * Refresh Timer Register (MPDDRC_RTR):
+	 */
+	writel(mpddr_value->rtr, &mpddr->rtr);
+
+	return 0;
+}