diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2015-01-01 22:04:34 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-14 14:56:40 +0100 |
| commit | 213480e12d880ef6782f56f1af95469b48cca539 (patch) | |
| tree | e6bc90e7c39254d5cc2981b0115781ef23b1ea23 /arch/arm | |
| parent | 213dcbfdeb3bdafad48cb330793fa870efef77f0 (diff) | |
sunxi: video: Add lvds support
Add support for lvds lcd panels
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/display.h | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 |
3 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 64b5c389e5..70b789e8e8 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -284,6 +284,8 @@ struct sunxi_ccm_reg { /* Enable / disable both ch1 sclk1 and sclk2 at the same time */ #define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15) +#define CCM_LVDS_CTRL_RST (1 << 0) + #define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) #define CCM_HDMI_CTRL_PLL_MASK (3 << 24) #define CCM_HDMI_CTRL_PLL3 (0 << 24) diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h index 5ce355d7b0..2ac8a879df 100644 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ b/arch/arm/include/asm/arch-sunxi/display.h @@ -91,6 +91,9 @@ struct sunxi_lcdc_reg { u8 res3[0x44]; /* 0xac */ u32 tcon1_io_polarity; /* 0xf0 */ u32 tcon1_io_tristate; /* 0xf4 */ + u8 res4[0x128]; /* 0xf8 */ + u32 lvds_ana0; /* 0x220 */ + u32 lvds_ana1; /* 0x224 */ }; struct sunxi_hdmi_reg { @@ -244,12 +247,21 @@ struct sunxi_tve_reg { #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) +#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) +#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0 (0 << 28) +#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60 (1 << 28) +#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE120 (2 << 28) #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16) +#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 +#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) +#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) +#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) /* * HDMI register constants. diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 9438f5a262..71cc879c2b 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -151,6 +151,7 @@ enum sunxi_gpio_number { #define SUNXI_GPC6_SDC2 3 #define SUNXI_GPD0_LCD0 2 +#define SUNXI_GPD0_LVDS0 3 #define SUNXI_GPF0_SDC0 2 |