diff options
| author | Zhichun Hua <zhichun.hua@freescale.com> | 2015-06-29 15:49:37 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-07-20 11:44:40 -0700 |
| commit | 21a257b9b3b29ddb1445fdafe12e05727080a198 (patch) | |
| tree | 87ea425ec314d57771e74a0200c5ad0684329541 /arch/arm | |
| parent | 25195600173e618b1cf693bcf38d48973e3a08fb (diff) | |
armv8: Fix TCR macros for shareability attribute
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b9cb52965..04fa0be64c 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -93,8 +93,8 @@ #define TCR_ORGN_WBNWA (3 << 10) #define TCR_ORGN_MASK (3 << 10) #define TCR_SHARED_NON (0 << 12) -#define TCR_SHARED_OUTER (1 << 12) -#define TCR_SHARED_INNER (2 << 12) +#define TCR_SHARED_OUTER (2 << 12) +#define TCR_SHARED_INNER (3 << 12) #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) |