Merge branch '2019-06-05-master-imports'

- More DaVinci fixes
- BuR platform fix

8 files changed, 286 insertions, 1083 deletions

diff --git a/arch/arm/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/dts/imx6-logicpd-baseboard.dtsi
index 303c09334b..c40a7af6eb 100644
--- a/arch/arm/dts/imx6-logicpd-baseboard.dtsi
+++ b/arch/arm/dts/imx6-logicpd-baseboard.dtsi
@@ -1,45 +1,6 @@
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
 
 / {
 	keyboard {
@@ -68,6 +29,7 @@
 			debounce-interval = <10>;
 			wakeup-source;
 		};
+
 		btn3 {
 			gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
 			label = "btn3";
@@ -81,7 +43,7 @@
 	leds {
 		compatible = "gpio-leds";
 
-		gen_led0 {
+		gen-led0 {
 			label = "led0";
 			pinctrl-names = "default";
 			pinctrl-0 = <&pinctrl_led0>;
@@ -89,25 +51,27 @@
 			linux,default-trigger = "cpu0";
 		};
 
-		gen_led1 {
+		gen-led1 {
 			label = "led1";
 			gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
 		};
 
-		gen_led2 {
+		gen-led2 {
 			label = "led2";
 			gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
-		gen_led3 {
+		gen-led3 {
 			label = "led3";
 			gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "default-on";
 		};
 	};
 
-	reg_usb_otg_vbus: regulator-otg-vbus@0 {
+	reg_usb_otg_vbus: regulator-otg-vbus {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usb_otg>;
 		compatible = "regulator-fixed";
 		regulator-name = "usb_otg_vbus";
 		regulator-min-microvolt = <5000000>;
@@ -116,14 +80,19 @@
 		enable-active-high;
 	};
 
-	reg_usb_h1_vbus: regulator-usbh1vbus@1 {
+	reg_usb_h1_vbus: regulator-usb-h1-vbus {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
 		compatible = "regulator-fixed";
 		regulator-name = "usb_h1_vbus";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <70000>;
+		enable-active-high;
 	};
 
-	reg_3v3: regulator-3v3@2 {
+	reg_3v3: regulator-3v3 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_3v3>;
 		compatible = "regulator-fixed";
@@ -131,13 +100,14 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <70000>;
 		enable-active-high;
 		regulator-always-on;
 	};
 
-	reg_enet: regulator-ethernet@3 {
+	reg_enet: regulator-ethernet {
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_enet_pwr>;
+		pinctrl-0 = <&pinctrl_reg_enet>;
 		compatible = "regulator-fixed";
 		regulator-name = "ethernet-supply";
 		regulator-min-microvolt = <3300000>;
@@ -148,7 +118,7 @@
 		vin-supply = <&sw4_reg>;
 	};
 
-	reg_audio: regulator-audio@4 {
+	reg_audio: regulator-audio {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_audio>;
 		compatible = "regulator-fixed";
@@ -157,11 +127,10 @@
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
-		regulator-always-on;
 		vin-supply = <&reg_3v3>;
 	};
 
-	reg_hdmi: regulator-hdmi@5 {
+	reg_hdmi: regulator-hdmi {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_hdmi>;
 		compatible = "regulator-fixed";
@@ -173,7 +142,7 @@
 		vin-supply = <&reg_3v3>;
 	};
 
-	reg_uart3: regulator-uart3@6 {
+	reg_uart3: regulator-uart3 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_uart3>;
 		compatible = "regulator-fixed";
@@ -184,7 +153,7 @@
 		vin-supply = <&reg_3v3>;
 	};
 
-	reg_1v8: regulator-1v8@7 {
+	reg_1v8: regulator-1v8 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_1v8>;
 		compatible = "regulator-fixed";
@@ -195,21 +164,21 @@
 		vin-supply = <&reg_3v3>;
 	};
 
-	reg_pcie: regulator@8 {
+	reg_pcie: regulator-pcie {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pcie_reg>;
-		regulator-name = "MPCIE_3V3";
+		pinctrl-0 = <&pinctrl_reg_pcie>;
+		regulator-name = "mpcie_3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
 
-	mipi_pwr: regulator@9 {
+	reg_mipi: regulator-mipi {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_mipi_pwr>;
+		pinctrl-0 = <&pinctrl_reg_mipi>;
 		regulator-name = "mipi_pwr_en";
 		regulator-min-microvolt = <2800000>;
 		regulator-max-microvolt = <2800000>;
@@ -221,7 +190,7 @@
 		compatible = "fsl,imx-audio-wm8962";
 		model = "wm8962-audio";
 		ssi-controller = <&ssi2>;
-		audio-codec = <&codec>;
+		audio-codec = <&wm8962>;
 		audio-routing =
 			"Headphone Jack", "HPOUTL",
 			"Headphone Jack", "HPOUTR",
@@ -246,34 +215,10 @@
 	status = "disabled";
 };
 
-&pwm3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm3>;
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
-	status = "okay";
-};
-
-&usbh1 {
-	vbus-supply = <&reg_usb_h1_vbus>;
-	status = "okay";
-};
-
-&usbotg {
-	vbus-supply = <&reg_usb_otg_vbus>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg>;
-	disable-over-current;
-	status = "okay";
-};
-
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-reset-duration = <10>;
 	phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
 	phy-supply = <&reg_enet>;
@@ -282,23 +227,13 @@
 	status = "okay";
 };
 
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	no-1-8-v;
-	keep-power-in-suspend;
-	status = "okay";
-};
-
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c1>;
 	clock-frequency = <400000>;
 	status = "okay";
 
-	codec: wm8962@1a {
+	wm8962: audio-codec@1a {
 		compatible = "wlf,wm8962";
 		reg = <0x1a>;
 		clocks = <&clks IMX6QDL_CLK_CKO>;
@@ -330,9 +265,9 @@
 		reg = <0x10>;
 		clocks = <&clks IMX6QDL_CLK_CKO>;
 		clock-names = "xclk";
-		DOVDD-supply = <&mipi_pwr>;
-		AVDD-supply = <&mipi_pwr>;
-		DVDD-supply = <&mipi_pwr>;
+		DOVDD-supply = <&reg_mipi>;
+		AVDD-supply = <&reg_mipi>;
+		DVDD-supply = <&reg_mipi>;
 		reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 		powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
 
@@ -361,6 +296,11 @@
 	};
 };
 
+&ipu1_csi1_from_mipi_vc1 {
+	clock-lanes = <0>;
+	data-lanes = <1 2>;
+};
+
 &mipi_csi {
 	status = "okay";
 
@@ -379,17 +319,52 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
 	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
-	status = "okay";
 	vpcie-supply = <&reg_pcie>;
-	/* fsl,max-link-speed = <2>; */
+	status = "okay";
+};
+
+&pwm3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
 };
 
 &ssi2 {
 	status = "okay";
 };
 
-&iomuxc {
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	status = "okay";
+};
 
+&usbh1 {
+	vbus-supply = <&reg_usb_h1_vbus>;
+	status = "okay";
+};
+
+&usbotg {
+	vbus-supply = <&reg_usb_otg_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	disable-over-current;
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	vmmc-supply = <&reg_3v3>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&iomuxc {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
@@ -399,21 +374,49 @@
 		>;
 	};
 
-	pinctrl_i2c1: i2c1 {
+	pinctrl_ecspi1: ecspi1grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D21__I2C1_SCL	0x4001b8b1
-			MX6QDL_PAD_EIM_D28__I2C1_SDA	0x4001b8b1
+			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
+			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
+			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
+			MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0		0x100b1
 		>;
 	};
 
-	pinctrl_enet_pwr: enet_pwr {
+	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
+			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0	/* ENET_INT */
+			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24	0x1b0b0	/* ETHR_nRST */
 		>;
 	};
 
-	pinctrl_mipi_pwr: pwr_mipi {
-		fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D21__I2C1_SCL	0x4001b8b1
+			MX6QDL_PAD_EIM_D28__I2C1_SDA	0x4001b8b1
+		>;
+	};
+
+	pinctrl_led0: led0grp {
+	    fsl,pins = <
+		MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0
+	    >;
 	};
 
 	pinctrl_ov5640: ov5640grp {
@@ -423,174 +426,132 @@
 		>;
 	};
 
-	pinctrl_reg_hdmi: reg_hdmi {
+	pinctrl_pcf8574: pcf8575grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D20__GPIO3_IO20	0x1b0b0
+			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
 		>;
 	};
 
-	pinctrl_uart3: uart3grp {
+	pinctrl_pcie: pciegrp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
-			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
-			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
-			MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
+			MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
+			MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
 		>;
 	};
 
-	pinctrl_usbotg: usbotggrp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_1__USB_OTG_ID	0xd17059
-			MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
-		>;
+	pinctrl_pwm3: pwm3grp {
+	    fsl,pins = <
+		MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+	    >;
 	};
 
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
-			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
-			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
-			MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0		0x100b1
-		>;
+	pinctrl_reg_1v8: reg1v8grp {
+	    fsl,pins = <
+		MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x1b0b0
+	    >;
 	};
 
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
-			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17069
-			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10069
-			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17069
-			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17069
-			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17069
-			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17069
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
-			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170b9
-			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100b9
-			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
-			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
-			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
-			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
-		>;
+	pinctrl_reg_3v3: reg3v3grp {
+	    fsl,pins = <
+		MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b0
+	    >;
 	};
 
-	pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
+	pinctrl_reg_audio: reg-audiogrp {
 		fsl,pins = <
-			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
-			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170f9
-			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100f9
-			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
-			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
-			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
-			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
+			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 		>;
 	};
 
-	pinctrl_enet: enetgrp {
+	pinctrl_reg_enet: reg-enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
-			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
-			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
-			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
-			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0	/* ENET_INT */
-			MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24	0x1b0b0	/* ETHR_nRST */
+			MX6QDL_PAD_EIM_D31__GPIO3_IO31	0x1b0b0
 		>;
 	};
 
-	pinctrl_reg_audio: audio-reg {
+	pinctrl_reg_hdmi: reg-hdmigrp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+			MX6QDL_PAD_EIM_D20__GPIO3_IO20	0x1b0b0
 		>;
 	};
 
-	pinctrl_pcie: pcie {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
-			MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
-		>;
+	pinctrl_reg_mipi: reg-mipigrp {
+		fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
 	};
 
-	pinctrl_pcie_reg: pciereggrp {
+	pinctrl_reg_pcie: reg-pciegrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_2__GPIO1_IO02	0x1b0b0
 			>;
 	};
 
-	pinctrl_pcf8574: pcf8575-pins {
+	pinctrl_reg_uart3: reguart3grp {
+	    fsl,pins = <
+		MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
+	    >;
+	};
+
+	pinctrl_reg_usb_h1_vbus: usbh1grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0
 		>;
 	};
 
-	pinctrl_lcd: lcdgrp {
+	pinctrl_reg_usb_otg: reg-usb-otggrp {
 		fsl,pins = <
-			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10	/* R_LCD_DCLK */
-			MX6QDL_PAD_DI0_PIN15__GPIO4_IO17	0x100b0	/* R_LCD_PANEL_PWR */
-			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02	0x10	/* R_LCD_HSYNC */
-			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03	0x10	/* R_LCD_VSYNC */
-			MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04	0x10	/* R_LCD_MDISP */
-			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
-			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
-			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
-			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
-			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
-			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
-			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
-			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
-			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
-			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
-			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
-			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
-			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
-			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
-			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
-			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
 		>;
 	};
 
-	pinctrl_pwm3: pwm3grp {
+	pinctrl_uart3: uart3grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
+			MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
+			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
+			MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
 		>;
 	};
 
-	pinctrl_reg_uart3: uart3reg {
+	pinctrl_usbotg: usbotggrp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
+			MX6QDL_PAD_GPIO_1__USB_OTG_ID	0xd17059
 		>;
 	};
 
-	pinctrl_reg_3v3: reg-3v3 {
+	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b0
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17069
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10069
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17069
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17069
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17069
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17069
 		>;
 	};
 
-	pinctrl_reg_1v8: reg-1v8 {
+	pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D30__GPIO3_IO30		0x1b0b0
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170b9
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100b9
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170b9
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170b9
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170b9
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170b9
 		>;
 	};
 
-	pinctrl_led0: led0 {
+	pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0
+			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* CD */
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x170f9
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x100f9
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x170f9
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x170f9
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x170f9
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x170f9
 		>;
 	};
+
 };
diff --git a/arch/arm/dts/imx6-logicpd-som.dtsi b/arch/arm/dts/imx6-logicpd-som.dtsi
index 3fc50babf0..7ceae35732 100644
--- a/arch/arm/dts/imx6-logicpd-som.dtsi
+++ b/arch/arm/dts/imx6-logicpd-som.dtsi
@@ -1,16 +1,6 @@
-/*
- * Copyright 2018 Logic PD
- * This file is adapted from imx6qdl-sabresd.dtsi.
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
@@ -20,7 +10,8 @@
 		stdout-path = &uart1;
 	};
 
-	memory {
+	memory@10000000 {
+		device_type = "memory";
 		reg = <0x10000000 0x80000000>;
 	};
 
@@ -35,17 +26,6 @@
 	};
 };
 
-/* Reroute power feeding the CPU to come from the external PMIC */
-&reg_arm
-{
-	vin-supply = <&sw1a_reg>;
-};
-
-&reg_soc
-{
-	vin-supply = <&sw1c_reg>;
-};
-
 &clks {
 	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
@@ -56,8 +36,8 @@
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
-	status = "okay";
 	nand-on-flash-bbt;
+	status = "okay";
 };
 
 &i2c3 {
@@ -66,7 +46,7 @@
 	pinctrl-0 = <&pinctrl_i2c3>;
 	status = "okay";
 
-	pmic: pfuze100@08 {
+	pfuze100: pmic@8 {
 		compatible = "fsl,pfuze100";
 		reg = <0x08>;
 
@@ -94,20 +74,19 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-name = "gen_3v3";
 				regulator-boot-on;
-				/* regulator-always-on; */
 			};
 
 			sw3a_reg: sw3a {
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1975000>;
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
 				regulator-name = "sw3a_vddr";
 				regulator-boot-on;
 				regulator-always-on;
 			};
 
 			sw3b_reg: sw3b {
-				regulator-min-microvolt = <400000>;
-				regulator-max-microvolt = <1975000>;
+				regulator-min-microvolt = <1350000>;
+				regulator-max-microvolt = <1350000>;
 				regulator-name = "sw3b_vddr";
 				regulator-boot-on;
 				regulator-always-on;
@@ -152,8 +131,8 @@
 
 			vgen3_reg: vgen3 {
 				regulator-name = "gen_vadj_0";
-				regulator-min-microvolt = <3000000>;
-				regulator-max-microvolt = <3000000>;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
 			};
 
 			vgen4_reg: vgen4 {
@@ -164,8 +143,8 @@
 			};
 
 			vgen5_reg: vgen5 {
-				regulator-name = "gen_adj_1";
-				regulator-min-microvolt = <3300000>;
+				regulator-name = "gen_vadj_1";
+				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-always-on;
 			};
@@ -185,44 +164,75 @@
 		};
 	};
 
-	temp_sense0: tmp102@4a {
+	temperature-sensor@49 {
 		compatible = "ti,tmp102";
-		reg = <0x4a>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_tempsense>;
+		reg = <0x49>;
 		interrupt-parent = <&gpio6>;
 		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 		#thermal-sensor-cells = <1>;
 	};
 
-	temp_sense1: tmp102@49 {
+	temperature-sensor@4a {
 		compatible = "ti,tmp102";
-		reg = <0x49>;
+		reg = <0x4a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_tempsense>;
 		interrupt-parent = <&gpio6>;
 		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 		#thermal-sensor-cells = <1>;
 	};
 
-	mfg_eeprom: at24@51 {
+	eeprom@51 {
 		compatible = "atmel,24c64";
 		pagesize = <32>;
-		read-only;
+		read-only;	/* Manufacturing EEPROM programmed at factory */
 		reg = <0x51>;
 	};
 
-	user_eeprom: at24@52 {
+	eeprom@52 {
 		compatible = "atmel,24c64";
 		pagesize = <32>;
 		reg = <0x52>;
 	};
 };
 
+/* Reroute power feeding the CPU to come from the external PMIC */
+&reg_arm
+{
+	vin-supply = <&sw1a_reg>;
+};
+
+&reg_soc
+{
+	vin-supply = <&sw1c_reg>;
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	pinctrl_hog: hoggrp {
+	pinctrl_gpmi_nand: gpmi-nandgrp {
 		fsl,pins = <
+			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0x0b0b1
+			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0x0b0b1
+			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0x0b0b1
+			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0x0b000
+			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0x0b0b1
+			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0x0b0b1
+			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0x0b0b1
+			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0x0b0b1
+			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0x0b0b1
+			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0x0b0b1
+			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0x0b0b1
+			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0x0b0b1
+			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0x0b0b1
+			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0x0b0b1
+			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0x0b0b1
+		>;
+	};
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <	/* Enable ARM Debugger */
 			MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL	0x1b0b0
 			MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO	0x1b0b0
 			MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00	0x1b0b0
@@ -246,30 +256,16 @@
 		>;
 	};
 
-	pinctrl_gpmi_nand: gpminandgrp {
+	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
-			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0x0b0b1
-			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0x0b0b1
-			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0x0b0b1
-			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0x0b000
-			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0x0b0b1
-			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0x0b0b1
-			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0x0b0b1
-			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0x0b0b1
-			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0x0b0b1
-			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0x0b0b1
-			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0x0b0b1
-			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0x0b0b1
-			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0x0b0b1
-			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0x0b0b1
-			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0x0b0b1
+			MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
+			MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
 		>;
 	};
 
-	pinctrl_i2c3: i2c3grp {
+	pinctrl_tempsense: tempsensegrp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
-			MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
+			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0
 		>;
 	};
 
@@ -282,7 +278,7 @@
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD3_RST__GPIO7_IO08	0x13059	/* BT_EN */
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x13059	/* BT_EN */
 			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
 			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
 			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
@@ -313,12 +309,6 @@
 			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00	0x17059 /* WLAN_EN */
 		>;
 	};
-
-	pinctrl_tempsense: tempsensegrp {
-		fsl,pins = <
-			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0	/* Temp Sense Alert */
-		>;
-	};
 };
 
 &snvs_poweroff {
@@ -334,8 +324,9 @@
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2>;
-	status = "okay";
 	uart-has-rtscts;
+	status = "okay";
+
 	bluetooth {
 		compatible = "ti,wl1837-st";
 		enable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
@@ -347,9 +338,9 @@
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	non-removable;
 	keep-power-in-suspend;
-	enable-sdio-wakeup;
-	status = "okay";
+	wakeup-source;
 	vmmc-supply = <&sw2_reg>;
+	status = "okay";
 };
 
 &usdhc3 {
@@ -360,9 +351,10 @@
 	keep-power-in-suspend;
 	wakeup-source;
 	vmmc-supply = <&reg_wl18xx_vmmc>;
-	status = "okay";
 	#address-cells = <1>;
 	#size-cells = <0>;
+	status = "okay";
+
 	wlcore: wlcore@2 {
 		  compatible = "ti,wl1837";
 		  reg = <2>;
diff --git a/arch/arm/dts/imx6q-logicpd.dts b/arch/arm/dts/imx6q-logicpd.dts
index dcea784477..45eb0b7f75 100644
--- a/arch/arm/dts/imx6q-logicpd.dts
+++ b/arch/arm/dts/imx6q-logicpd.dts
@@ -1,45 +1,6 @@
-/*
- * Copyright 2018 Logic PD, Inc.
- * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2019 Logic PD, Inc.
 
 /dts-v1/;
 #include "imx6q.dtsi"
@@ -47,10 +8,10 @@
 #include "imx6-logicpd-baseboard.dtsi"
 
 / {
-	model = "Logic PD i.MX6QD SOM-M3 (HDMI)";
+	model = "Logic PD i.MX6QD SOM-M3";
 	compatible = "fsl,imx6q";
 
-	backlight: backlight_lvds {
+	backlight: backlight-lvds {
 		compatible = "pwm-backlight";
 		pwms = <&pwm3 0 20000>;
 		brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -58,6 +19,16 @@
 		power-supply = <&reg_lcd>;
 	};
 
+	panel-lvds0 {
+		compatible = "okaya,rs800480t-7x0gp";
+
+		port {
+			panel_in_lvds0: endpoint {
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+
 	reg_lcd: regulator-lcd {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_lcd_reg>;
@@ -72,7 +43,7 @@
 		startup-delay-us = <500000>;
 	};
 
-	lcd_reset: lcd_reset {
+	reg_lcd_reset: regulator-lcd-reset {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_lcd_reset>;
 		compatible = "regulator-fixed";
@@ -84,17 +55,17 @@
 		regulator-always-on;
 		vin-supply = <&reg_lcd>;
 	};
+};
 
-	panel-lvds0 {
-		compatible = "ampire,am800480b3tmqw";
-		backlight = <&backlight>;
-
-		port {
-			panel_in_lvds0: endpoint {
-				remote-endpoint = <&lvds0_out>;
-			};
-		};
-	};
+&clks {
+	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+			  <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
 };
 
 &hdmi {
@@ -102,22 +73,6 @@
 	status = "okay";
 };
 
-&i2c1 {
-	ili_touch: ilitouch@26 {
-		compatible = "ili,ili2117a";
-		reg = <0x26>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_touchscreen>;
-		interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_RISING>;
-		ili2117a,poll-period = <10>;
-		ili2117a,max-touch = <2>;
-	};
-};
-
-&reg_hdmi {
-	regulator-always-on;
-};
-
 &ldb {
 	status = "okay";
 
@@ -128,7 +83,6 @@
 
 		port@4 {
 			reg = <4>;
-
 			lvds0_out: endpoint {
 				remote-endpoint = <&panel_in_lvds0>;
 			};
@@ -137,23 +91,12 @@
 
 };
 
-&clks {
-	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
-			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
-			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
-			  <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
-	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
-				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
-				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
-				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
-};
-
 &pwm3 {
 	status = "okay";
 };
 
-&usdhc2 {
-	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+&reg_hdmi {
+	regulator-always-on;	/* Without this, the level shifter on HDMI doesn't turn on */
 };
 
 &iomuxc {
@@ -165,7 +108,7 @@
 
 	pinctrl_lcd_reset: lcdreset {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_A25__GPIO5_IO02      0x100b0	/* LCD_nRESET */
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02	0x100b0	/* LCD_nRESET */
 		>;
 	};
 
@@ -175,4 +118,3 @@
 		>;
 	};
 };
-
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 61e84e5129..adc50922c8 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -134,7 +134,6 @@ source "board/davinci/da8xxevm/Kconfig"
 source "board/lego/ev3/Kconfig"
 
 config SPL_LDSCRIPT
-	default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
 	default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
 
 endif
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 6887fe05dd..ed88274072 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -18,7 +18,3 @@ obj-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
 obj-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
 obj-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y	+= lowlevel_init.o
-endif
diff --git a/arch/arm/mach-davinci/lowlevel_init.S b/arch/arm/mach-davinci/lowlevel_init.S
deleted file mode 100644
index b82dafad2b..0000000000
--- a/arch/arm/mach-davinci/lowlevel_init.S
+++ /dev/null
@@ -1,692 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- */
-
-#include <config.h>
-
-#define MDSTAT_STATE	0x3f
-
-.globl	lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
-	/*-------------------------------------------------------*
-	 * Mask all IRQs by setting all bits in the EINT default *
-	 *-------------------------------------------------------*/
-	mov	r1, $0
-	ldr	r0, =EINT_ENABLE0
-	str	r1, [r0]
-	ldr	r0, =EINT_ENABLE1
-	str	r1, [r0]
-
-	/*------------------------------------------------------*
-	 * Put the GEM in reset					*
-	 *------------------------------------------------------*/
-
-	/* Put the GEM in reset */
-	ldr	r8, PSC_GEM_FLAG_CLEAR
-	ldr	r6, MDCTL_GEM
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x02
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x02
-	bne	checkStatClkStopGem
-
-	/* Check for GEM Reset Completion */
-checkGemStatClkStop:
-	ldr	r6, MDSTAT_GEM
-	ldr	r7, [r6]
-	ands	r7, r7, $0x100
-	bne	checkGemStatClkStop
-
-	/* Do this for enabling a WDT initiated reset this is a workaround
-	   for a chip bug.  Not required under normal situations */
-	ldr	r6, P1394
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * Enable L1 & L2 Memories in Fast mode                 *
-	 *------------------------------------------------------*/
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, MMARG_BRF0
-	ldr	r10, MMARG_BRF0_VAL
-	str	r10, [r6]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*------------------------------------------------------*
-	 * DDR2 PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r10, $0
-	ldr	r6, PLL2_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r10, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-WaitPPL2Loop:
-	subs	r10, r10, $1
-	bne	WaitPPL2Loop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL2_PLLM
-	mov	r2, $0x17	/* 162 MHz */
-	str	r2, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV2
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/* Program the PLL2 Divisor Value */
-	ldr	r6, PLL2_DIV1
-	mov	r4, $0x0b	/* 54 MHz */
-	str	r4, [r6]
-
-	/* PLL2 DIV2 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV2
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop_0:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop_0
-
-	/* PLL2 DIV1 MMR */
-	ldr	r8, PLL2_DIV_MASK
-	ldr	r6, PLL2_DIV1
-	ldr	r9, [r6]
-	and	r8, r8, r9
-	mov	r9, $0x01
-	mov	r9, r9, lsl $15
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Program the GOSET bit to take new divider values */
-	ldr	r6, PLL2_PLLCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Wait for Done */
-	ldr	r6, PLL2_PLLSTAT
-doneLoop:
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	doneLoop
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0x218
-ResetPPL2Loop:
-	subs	r10, r10, $1
-	bne	ResetPPL2Loop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-PLL2Lock:
-	subs	r10, r10, $1
-	bne	PLL2Lock
-
-	/* Enable the PLL */
-	ldr	r6, PLL2_CTL
-	ldr	r8, [r6]
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $MDSTAT_STATE
-	cmp	r7, $0x03
-	bne	checkDDRStatClkStop
-
-	/*------------------------------------------------------*
-	 * Program DDR2 MMRs for 162MHz Setting			*
-	 *------------------------------------------------------*/
-
-	/* Program PHY Control Register */
-	ldr	r6, DDRCTL
-	ldr	r7, DDRCTL_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM Bank Config Register */
-	ldr	r6, SDCFG
-	ldr	r7, SDCFG_VAL
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-0 Config Register */
-	ldr	r6, SDTIM0
-	ldr	r7, SDTIM0_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program SDRAM TIM-1 Config Register */
-	ldr	r6, SDTIM1
-	ldr	r7, SDTIM1_VAL_162MHz
-	str	r7, [r6]
-
-	/* Program the SDRAM Bank Config Control Register */
-	ldr	r10, MASK_VAL
-	ldr	r8, SDCFG
-	ldr	r9, SDCFG_VAL
-	and	r9, r9, r10
-	str	r9, [r8]
-
-	/* Program SDRAM SDREF Config Register */
-	ldr	r6, SDREF
-	ldr	r7, SDREF_VAL
-	str	r7, [r6]
-
-	/*------------------------------------------------------*
-	 * Issue Soft Reset to DDR Module			*
-	 *------------------------------------------------------*/
-
-	/* Issue a Dummy DDR2 read/write */
-	ldr	r8, DDR2_START_ADDR
-	ldr	r7, DUMMY_VAL
-	str	r7, [r8]
-	ldr	r7, [r8]
-
-	/* Shut down the DDR2 LPSC Module */
-	ldr	r8, PSC_FLAG_CLEAR
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, r8
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkStop2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $MDSTAT_STATE
-	cmp	r7, $0x01
-	bne	checkDDRStatClkStop2
-
-	/*------------------------------------------------------*
-	 * Turn DDR2 Controller Clocks On			*
-	 *------------------------------------------------------*/
-
-	/* Enable the DDR2 LPSC Module */
-	ldr	r6, MDCTL_DDR2
-	ldr	r7, [r6]
-	orr	r7, r7, $0x03
-	str	r7, [r6]
-
-	/* Enable the Power Domain Transition Command */
-	ldr	r6, PTCMD
-	ldr	r7, [r6]
-	orr	r7, r7, $0x01
-	str	r7, [r6]
-
-	/* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
-	ldr	r6, PTSTAT
-	ldr	r7, [r6]
-	ands	r7, r7, $0x01
-	bne	checkStatClkEn2
-
-	/* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
-	ldr	r6, MDSTAT_DDR2
-	ldr	r7, [r6]
-	and	r7, r7, $MDSTAT_STATE
-	cmp	r7, $0x03
-	bne	checkDDRStatClkEn2
-
-	/*  DDR Writes and Reads */
-	ldr	r6, CFGTEST
-	mov	r3, $0x01
-	str	r3, [r6]
-
-	/*------------------------------------------------------*
-	 * System PLL Initialization				*
-	 *------------------------------------------------------*/
-
-	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
-	mov	r2, $0
-	ldr	r6, PLL1_CTL
-	ldr	r7, PLL_CLKSRC_MASK
-	ldr	r8, [r6]
-	and	r8, r8, r7
-	mov	r9, r2, lsl $8
-	orr	r8, r8, r9
-	str	r8, [r6]
-
-	/* Select the PLLEN source */
-	ldr	r7, PLL_ENSRC_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Bypass the PLL */
-	ldr	r7, PLL_BYPASS_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
-	mov	r10, $0x20
-
-WaitLoop:
-	subs	r10, r10, $1
-	bne	WaitLoop
-
-	/* Reset the PLL */
-	ldr	r7, PLL_RESET_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Disable the PLL */
-	orr	r8, r8, $0x10
-	str	r8, [r6]
-
-	/* Power up the PLL */
-	ldr	r7, PLL_PWRUP_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Enable the PLL from Disable Mode */
-	ldr	r7, PLL_DISABLE_ENABLE_MASK
-	and	r8, r8, r7
-	str	r8, [r6]
-
-	/* Program the PLL Multiplier */
-	ldr	r6, PLL1_PLLM
-	mov	r3, $0x15	/* For 594MHz */
-	str	r3, [r6]
-
-	/* Wait for PLL to Reset Properly */
-	mov	r10, $0xff
-
-ResetLoop:
-	subs	r10, r10, $1
-	bne	ResetLoop
-
-	/* Bring PLL out of Reset */
-	ldr	r6, PLL1_CTL
-	orr	r8, r8, $0x08
-	str	r8, [r6]
-
-	/* Wait for PLL to Lock */
-	ldr	r10, PLL_LOCK_COUNT
-
-PLL1Lock:
-	subs	r10, r10, $1
-	bne	PLL1Lock
-
-	/* Enable the PLL */
-	orr	r8, r8, $0x01
-	str	r8, [r6]
-
-	nop
-	nop
-	nop
-	nop
-
-	/*------------------------------------------------------*
-	 * AEMIF configuration for NOR Flash (double check)     *
-	 *------------------------------------------------------*/
-	ldr	r0, _PINMUX0
-	ldr	r1, _DEV_SETTING
-	str	r1, [r0]
-
-	ldr	r0, WAITCFG
-	ldr	r1, WAITCFG_VAL
-	ldr	r2, [r0]
-	orr	r2, r2, r1
-	str	r2, [r0]
-
-	ldr	r0, ACFG3
-	ldr	r1, ACFG3_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG4
-	ldr	r1, ACFG4_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	ldr	r0, ACFG5
-	ldr	r1, ACFG5_VAL
-	ldr	r2, [r0]
-	and	r1, r2, r1
-	str	r1, [r0]
-
-	/*--------------------------------------*
-	 * VTP manual Calibration               *
-	 *--------------------------------------*/
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR0
-	str	r1, [r0]
-
-	ldr	r0, VTPIOCR
-	ldr	r1, VTP_MMR1
-	str	r1, [r0]
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTPLock:
-	subs	r10, r10, $1
-	bne	VTPLock
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0x01
-	str	r10, [r6]
-
-	ldr	r6, DDRVTPR
-	ldr	r7, [r6]
-	mov	r8, r7, LSL #32-10
-	mov	r8, r8, LSR #32-10        /* grab low 10 bits  */
-	ldr	r7, VTP_RECAL
-	orr	r8, r7, r8
-	ldr	r7, VTP_EN
-	orr	r8, r7, r8
-	str	r8, [r0]
-
-
-	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
-	ldr	r10, VTP_LOCK_COUNT
-VTP1Lock:
-	subs	r10, r10, $1
-	bne	VTP1Lock
-
-	ldr	r1, [r0]
-	ldr	r2, VTP_MASK
-	and	r2, r1, r2
-	str	r2, [r0]
-
-	ldr	r6, DFT_ENABLE
-	mov	r10, $0
-	str	r10, [r6]
-
-	/*
-	 * Call board-specific lowlevel init.
-	 * That MUST be present and THAT returns
-	 * back to arch calling code with "mov pc, lr."
-	 */
-	b	dv_board_init
-
-.ltorg
-
-_PINMUX0:
-	.word	0x01c40000		/* Device Configuration Registers */
-_PINMUX1:
-	.word	0x01c40004		/* Device Configuration Registers */
-
-_DEV_SETTING:
-	.word	0x00000c1f
-
-WAITCFG:
-	.word	0x01e00004
-WAITCFG_VAL:
-	.word	0
-ACFG3:
-	.word	0x01e00014
-ACFG3_VAL:
-	.word	0x3ffffffd
-ACFG4:
-	.word	0x01e00018
-ACFG4_VAL:
-	.word	0x3ffffffd
-ACFG5:
-	.word	0x01e0001c
-ACFG5_VAL:
-	.word	0x3ffffffd
-
-MDCTL_DDR2:
-	.word	0x01c41a34
-MDSTAT_DDR2:
-	.word	0x01c41834
-
-PTCMD:
-	.word	0x01c41120
-PTSTAT:
-	.word	0x01c41128
-
-EINT_ENABLE0:
-	.word	0x01c48018
-EINT_ENABLE1:
-	.word	0x01c4801c
-
-PSC_FLAG_CLEAR:
-	.word	0xffffffe0
-PSC_GEM_FLAG_CLEAR:
-	.word	0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
-	.word	0x200000e4
-DDRCTL_VAL:
-	.word	0x50006405
-SDREF:
-	.word	0x2000000c
-SDREF_VAL:
-	.word	0x000005c3
-SDCFG:
-	.word	0x20000008
-SDCFG_VAL:
-#ifdef	DDR_4BANKS
-	.word	0x00178622
-#elif defined DDR_8BANKS
-	.word	0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
-	.word	0x20000010
-SDTIM0_VAL_162MHz:
-	.word	0x28923211
-SDTIM1:
-	.word	0x20000014
-SDTIM1_VAL_162MHz:
-	.word	0x0016c722
-VTPIOCR:
-	.word	0x200000f0	/* VTP IO Control register */
-DDRVTPR:
-	.word	0x01c42030	/* DDR VPTR MMR */
-VTP_MMR0:
-	.word	0x201f
-VTP_MMR1:
-	.word	0xa01f
-DFT_ENABLE:
-	.word	0x01c4004c
-VTP_LOCK_COUNT:
-	.word	0x5b0
-VTP_MASK:
-	.word	0xffffdfff
-VTP_RECAL:
-	.word	0x08000
-VTP_EN:
-	.word	0x02000
-CFGTEST:
-	.word	0x80010000
-MASK_VAL:
-	.word	0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
-	.word	0x01c41a9c
-MDSTAT_GEM:
-	.word	0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
-	.word	0x01c41a20
-
-PLL_CLKSRC_MASK:
-	.word	0xfffffeff	/* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
-	.word	0xffffffdf	/* Select the PLLEN source */
-PLL_BYPASS_MASK:
-	.word	0xfffffffe	/* Put the PLL in BYPASS */
-PLL_RESET_MASK:
-	.word	0xfffffff7	/* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
-	.word	0xfffffffd	/* PLL Power up Mask Bit  */
-PLL_DISABLE_ENABLE_MASK:
-	.word	0xffffffef	/* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
-	.word	0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
-	.word	0x01c40900
-PLL1_PLLM:
-	.word	0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
-	.word	0x01c40d00
-PLL2_PLLM:
-	.word	0x01c40d10
-PLL2_DIV1:
-	.word	0x01c40d18
-PLL2_DIV2:
-	.word	0x01c40d1c
-PLL2_PLLCMD:
-	.word	0x01c40d38
-PLL2_PLLSTAT:
-	.word	0x01c40d3c
-PLL2_DIV_MASK:
-	.word	0xffff7fff
-
-MMARG_BRF0:
-	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
-	.word	0x00444400
-
-DDR2_START_ADDR:
-	.word	0x80000000
-DUMMY_VAL:
-	.word	0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
-	mov pc, lr
-#endif
diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c
index 103639e347..be3daa9bc0 100644
--- a/arch/arm/mach-davinci/spl.c
+++ b/arch/arm/mach-davinci/spl.c
@@ -31,9 +31,12 @@ void putc(char c)
 }
 #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
 
-void spl_board_init(void)
+void board_init_f(ulong dummy)
 {
 	arch_cpu_init();
+
+	spl_early_init();
+
 	preloader_console_init();
 }
 
diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c
index 2d25fc60a0..658ef8c1f1 100644
--- a/arch/arm/mach-omap2/omap3/board.c
+++ b/arch/arm/mach-omap2/omap3/board.c
@@ -34,6 +34,8 @@ static void omap3_invalidate_l2_cache_secure(void);
 #endif
 
 #ifdef CONFIG_DM_GPIO
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+/* Manually initialize GPIO banks when OF_CONTROL doesn't */
 static const struct omap_gpio_platdata omap34xx_gpio[] = {
 	{ 0, OMAP34XX_GPIO1_BASE },
 	{ 1, OMAP34XX_GPIO2_BASE },
@@ -51,7 +53,7 @@ U_BOOT_DEVICES(omap34xx_gpios) = {
 	{ "gpio_omap", &omap34xx_gpio[4] },
 	{ "gpio_omap", &omap34xx_gpio[5] },
 };
-
+#endif
 #else
 
 static const struct gpio_bank gpio_bank_34xx[6] = {