diff options
| author | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2014-08-08 08:41:15 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | 2014-10-09 14:45:03 +0900 |
| commit | 237faf095fb43abbed6e40266ef7efccc8b9308b (patch) | |
| tree | 4635d3f0042ce1ba74f2039199d302067f98d98e /arch/arm | |
| parent | 7d835803640e743a60572b49a736370c75f9cb44 (diff) | |
arm: rmobile: r8a7791: Fix initialize L2 cache
rmobile/lowlevel_init_ca15.S are common in r8a7790 and r8a7791 of
rmobile SoC. But L2 cache of r8a7791 does not use L2CTLR[5].
This adds fix to set L2CTLR [5] only when the r8a7790.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index dbb96ed194..5820e1a37a 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -53,7 +53,15 @@ do_lowlevel_init: cmp r1, #3 /* has already been set up */ bicne r0, r0, #0xe7 orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ - orrne r0, r0, #0x20 /* L2CTLR[5] */ + + ldr r2, =0xFF000044 /* PRR */ + ldr r1, [r2] + and r1, r1, #0x7F00 + lsrs r1, r1, #8 + cmp r1, #0x45 /* 0x45 is ID of r8a7790 */ + bne L2CTLR_5_SKIP + orrne r0, r0, #0x20 /* L2CTLR[5] */ +L2CTLR_5_SKIP: mcrne p15, 1, r0, c9, c0, 2 _exit_init_l2_a15: |