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authorPeng Fan <Peng.Fan@freescale.com>2015-08-17 16:10:59 +0800
committerStefano Babic <sbabic@denx.de>2015-09-02 15:34:12 +0200
commit2cd8cd06bb01f220f75d937f0371f591712f0295 (patch)
tree8a73be24fb0f8d1d6300090c357c3958810b659e /arch/arm
parent24139754f55e11a41bd90d0c8064a79228b573a3 (diff)
imx: mx6: ddr correct tRFC and tXS
To Chip density 4Gb, tRFC should be 300ns, see "Table 61 — Refresh parameters by device density" of JESD79-3E. tXS(min) is max(5nCK, tRFC(min) + 10ns). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/mx6/ddr.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 28fa3cf648..3ec3e791c9 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -357,8 +357,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
txs = DIV_ROUND_UP(170000, clkper) - 1;
break;
case 4: /* 4Gb per chip */
- trfc = DIV_ROUND_UP(260000, clkper) - 1;
- txs = DIV_ROUND_UP(270000, clkper) - 1;
+ trfc = DIV_ROUND_UP(300000, clkper) - 1;
+ txs = DIV_ROUND_UP(310000, clkper) - 1;
break;
case 8: /* 8Gb per chip */
trfc = DIV_ROUND_UP(350000, clkper) - 1;