Merge branch '2019-02-08-master-imports'

- bcm6345 watchdog, bcm63158/bcm963158 initial support.
- Various TI platform resyncs and improvements.
- FDT support in Android-format images.
- stm32mp1 improvements.

6 files changed, 182 insertions, 30 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0edb10003..455f06cfee 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -528,6 +528,12 @@ config ARCH_BCM283X
 	imply CMD_DM
 	imply FAT_WRITE
 
+config ARCH_BCM63158
+	bool "Broadcom BCM63158 family"
+	select DM
+	select OF_CONTROL
+	imply CMD_DM
+
 config ARCH_BCM6858
 	bool "Broadcom BCM6858 family"
 	select DM
@@ -1526,6 +1532,7 @@ source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/broadcom/bcm23550_w1d/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
+source "board/broadcom/bcm963158/Kconfig"
 source "board/broadcom/bcm968580xref/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
new file mode 100644
index 0000000000..6a3fbc9093
--- /dev/null
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include "skeleton64.dtsi"
+
+/ {
+	compatible = "brcm,bcm63158";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x0>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x1>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x2>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0x0 0x3>;
+			next-level-cache = <&l2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		l2: l2-cache0 {
+			compatible = "cache";
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0xbebc200>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+
+		uart0: serial@ff812000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0xff812000 0x0 0x1000>;
+			clock = <50000000>;
+
+			status = "disabled";
+		};
+
+		wdt1: watchdog@ff800480 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff800480 0x0 0x14>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt2: watchdog@ff8004c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff8004c0 0x0 0x14>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
+	};
+};
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index d78d34d213..23b80c67a6 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -81,5 +81,22 @@
 
 			status = "disabled";
 		};
+
+		wdt1: watchdog@ff802780 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff802780 0x0 0x14>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt2: watchdog@ff8027c0 {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x0 0xff8027c0 0x0 0x14>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt1>;
+		};
 	};
 };
diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts
new file mode 100644
index 0000000000..dc5afb5a24
--- /dev/null
+++ b/arch/arm/dts/bcm963158.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+/dts-v1/;
+
+#include "bcm63158.dtsi"
+
+/ {
+	model = "Broadcom bcm963158";
+	compatible = "broadcom,bcm963158", "brcm,bcm63158";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+	status = "okay";
+};
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index 4898483e1d..70bbf66704 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -39,6 +39,10 @@
 	};
 };
 
+&clk_hse {
+	st,digbypass;
+};
+
 &uart4_pins_a {
 	u-boot,dm-pre-reloc;
 	pins1 {
@@ -68,7 +72,6 @@
 	u-boot,dm-pre-reloc;
 };
 
-/* CLOCK init */
 &rcc {
 	st,clksrc = <
 		CLK_MPU_PLL1P
@@ -101,7 +104,7 @@
 		CLK_FMC_ACLK
 		CLK_QSPI_ACLK
 		CLK_ETH_DISABLED
-		CLK_SDMMC12_PLL3R
+		CLK_SDMMC12_PLL4P
 		CLK_DSI_DSIPLL
 		CLK_STGEN_HSE
 		CLK_USBPHY_HSE
@@ -110,7 +113,7 @@
 		CLK_SPI45_HSI
 		CLK_SPI6_HSI
 		CLK_I2C46_HSI
-		CLK_SDMMC3_PLL3R
+		CLK_SDMMC3_PLL4P
 		CLK_USBO_USBPHY
 		CLK_ADC_CKPER
 		CLK_CEC_LSE
@@ -121,17 +124,17 @@
 		CLK_UART35_HSI
 		CLK_UART6_HSI
 		CLK_UART78_HSI
-		CLK_SPDIF_PLL3Q
+		CLK_SPDIF_PLL4P
 		CLK_FDCAN_PLL4Q
 		CLK_SAI1_PLL3Q
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q
 		CLK_SAI4_PLL3Q
-		CLK_RNG1_CSI
-		CLK_RNG2_CSI
+		CLK_RNG1_LSI
+		CLK_RNG2_LSI
 		CLK_LPTIM1_PCLK1
 		CLK_LPTIM23_PCLK3
-		CLK_LPTIM45_PCLK3
+		CLK_LPTIM45_LSE
 	>;
 
 	/* VCO = 1300.0 MHz => P = 650 (CPU) */
@@ -148,16 +151,16 @@
 		u-boot,dm-pre-reloc;
 	};
 
-	/* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
+	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 	pll3: st,pll@2 {
-		cfg = < 2 97 3 15 7 PQR(1,1,1) >;
-		frac = < 0x9ba >;
+		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+		frac = < 0x1a04 >;
 		u-boot,dm-pre-reloc;
 	};
 
-	/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
+	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 	pll4: st,pll@3 {
-		cfg = < 5 126 8 8 8 PQR(1,1,1) >;
+		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 		u-boot,dm-pre-reloc;
 	};
 };
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index cc89d4a296..5909bbfa8f 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -19,33 +19,25 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 
 	/*
 	 * It is assumed that remoteproc device 1 is the corresponding
-	 * cortex A core which runs ATF. Make sure DT reflects the same.
+	 * Cortex-A core which runs ATF. Make sure DT reflects the same.
 	 */
 	ret = rproc_dev_init(1);
-	if (ret) {
-		printf("%s: ATF failed to Initialize on rproc: ret= %d\n",
-		       __func__, ret);
-		hang();
-	}
+	if (ret)
+		panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
+		      ret);
 
 	ret = rproc_load(1, spl_image->entry_point, 0x200);
-	if (ret) {
-		printf("%s: ATF failed to load on rproc: ret= %d\n",
-		       __func__, ret);
-		hang();
-	}
+	if (ret)
+		panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
 
-	/* Add an extra newline to differentiate the ATF logs from SPL*/
+	/* Add an extra newline to differentiate the ATF logs from SPL */
 	printf("Starting ATF on ARM64 core...\n\n");
 
 	ret = rproc_start(1);
-	if (ret) {
-		printf("%s: ATF failed to start on rproc: ret= %d\n",
-		       __func__, ret);
-		hang();
-	}
+	if (ret)
+		panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
 
-	debug("ATF started. Wait indefiniely\n");
+	debug("ATF started. Waiting indefinitely...\n");
 	while (1)
 		asm volatile("wfe");
 }