diff options
| author | Stefan Roese <sr@denx.de> | 2015-08-25 14:09:12 +0200 |
|---|---|---|
| committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-10-21 02:25:00 +0200 |
| commit | 42cc034f19d30a3e0f1a63788347e039315806a0 (patch) | |
| tree | 3cedc7016319e4e772470f451dc3ecc2cd8fc0b0 /arch/arm | |
| parent | 944c7a317675d8dbf082a2f144fec1139a5cb811 (diff) | |
arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL
When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 31 |
1 files changed, 19 insertions, 12 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index efd4d04ea8..895ad929b1 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -27,6 +27,14 @@ static struct mbus_win windows[] = { CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, }; +void lowlevel_init(void) +{ + /* + * Dummy implementation, we only need LOWLEVEL_INIT + * on Armada to configure CP15 in start.S / cpu_init_cp15() + */ +} + void reset_cpu(unsigned long ignored) { struct mvebu_system_registers *reg = @@ -214,7 +222,10 @@ static void setup_usb_phys(void) int arch_cpu_init(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X) +#if !defined(CONFIG_SPL_BUILD) + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + /* * Only with disabled MMU its possible to switch the base * register address on Armada 38x. Without this the SDRAM @@ -234,18 +245,14 @@ int arch_cpu_init(void) * configured the internal register base to the value used * in the macros / defines in the U-Boot header (soc.h). */ - if (mvebu_soc_family() == MVEBU_SOC_A38X) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - } + /* + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. + */ + icache_disable(); + dcache_disable(); + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); #endif /* |