diff options
| author | SRICHARAN R <r.sricharan@ti.com> | 2012-03-12 02:25:41 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-05-15 08:31:24 +0200 |
| commit | 47c50143aad7676ffa513bc395c49eb254a2c191 (patch) | |
| tree | 103d02fce462c21fb3970a507ed3f4171a966e1b /arch/arm | |
| parent | 087189fb54b49a4656255d60052ad047f974c7d6 (diff) | |
OMAP5: SRAM: Change the SRAM base address.
The full internal SRAM of size 128kb is public in the case of OMAP5 soc.
So change the base address accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 07546c92e6..10a973c1ed 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -249,7 +249,7 @@ struct omap5_sys_ctrl_regs { * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE * at 0x40304000(EMU base) so that our code works for both EMU and GP */ -#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 |